This is the first time I have designed a 4 layer board and the reading I have done says to use stitching vias for the differential pairs due to the stackup I am using. The stackup is as follows
I have pasted an image that I used for reference when designing my board. For context the board I am laying out is for a Raspberry Pi compute module 3 IO board. It is a section of pins from the SODIMM connector with traces going to a DSI display connector.
I am wondering if I really need 2 capacitors for each side of a pair or can I just put single capacitors between the pairs due to space limitations (as I have it laid out now). Also should I be getting the vias from the caps a little closer to the signal vias?
The capacitors are all 0402 size with 100nF value (X7R 10%).
Thanks in advance!