What the RL as view by this circuit

Question

^{simulate this circuit – Schematic created using CircuitLab}

In this condition, RL=infinity so the voltage gain of the output at the node R5 and Q1 can be obtain as below

$$A_v=\frac{4800}{450}=10.67$$

Verified with simulator which is in good agreement

^{simulate this circuit}

However, now the output is connected to a bypass capacitor of 5.3micro farad and my simulator showing a gain of only 3, understood as there is current flow into the 5.3micro farad capacitor that pull down the voltage gain and from youtube https://www.youtube.com/watch?v=-MyVscG-Pew&t=363s I understood the gain is gain is $$A_v=\frac{4800||R_{effective}}{r_e'+450}$$

Is the $$R_{effective}=R_7||R_8$$ so that theoretical value of $$A_v=3.73$$ or the calculation is actually more complicated than this?

Answer 1

Let's look at the 2nd stage.

The first thing to do is to work out the DC quiescent point for your 2nd stage. Assuming \$\beta\approx 200\$, I get \$I_{\text{B}_2}=\frac{V_{_\text{TH}}-V_\text{BE}}{R_{_\text{TH}}-\beta\cdot R_\text{E}}\approx 5.5\:\mu\text{A}\$ and therefore \$I_{\text{E}_2}\approx 1.1\:\text{mA}\$. This means \$r_e^{'}\approx 24\:\Omega\$. And if your frequency is \$1\:\text{kHz}\$, then \$X_\text{C}\approx 5.3\:\Omega\$. Reflected back to the base I get about \$5.9\:\text{k}\Omega\$. So the total load on the first stage is about \$5.9\:\text{k}\Omega\mid\mid 26\:\text{k}\Omega\mid\mid 2.9\:\text{k}\Omega\$ or about \$\approx 1.81\:\text{k}\Omega\$. This means that only about 27.4% of the 1st stage voltage gain is retained. About \$27.4\%\cdot 10.67\approx 2.92\$, or so.

Very close to what you measured with simulation.