I am designing the MIPS processor, this includes Data Memory and Instruction memory for testing.
I had a problem with IM synthesis covered in this question (How to make a synthesizable Instruction Memory in SystemVerilog?) and after rewriting it as adviced (ff with a
case statement) another problem occured.
The problem: Insruction in CPU has one cycle delay from the Program Counter. Thus, when branch instruction (number i) come, the Program Counter is already (i+1) and then come instr (i+1) and PC is PC_branch. How can I fix it? Delay is caused by this ff in IM. Code and waveforms are below.
always_ff @(posedge clk) begin case (addr) 32'd0 : rom_ff <= 32'h2408000F; // a = F 32'd1 : rom_ff <= 32'h240A0000; // res = 0 32'd2 : rom_ff <= 32'h01485021; // (*) res = res + a 32'd3 : rom_ff <= 32'h2508FFFF; // a = a - 1 32'd4 : rom_ff <= 32'h1500FFFD; // if (a != 0) goto (*) 32'd5 : rom_ff <= 32'hAC0A0ADD; default : rom_ff <= 32'h0; endcase end