2
\$\begingroup\$

The circuit diagram is taken from TI's LDO Basics. I don't understand how this circuit regulates the voltage, and neither do I know where I should start. But here's my attempt (with some values plugged in for better intuition):

  1. Supply a 2.5V \$ V_{REF} \$ to \$ V_- \$ of the opamp. By virtual short, \$ V_+ \$ or \$ V_{R2} \$ will also be 2.5V.
  2. Since \$ R_1 \$ and \$ R_2\$ forms a voltage divider, for \$ V_{R2} \$ to be 2.5V, \$ V_{OUT} \$ has to be 5V
  3. \$ V_{SD} \$ is also 5V (\$ V_{IN} - V_{OUT} \$)
  4. Any fluctuation or difference between \$ V_- \$ and \$ V_+ \$ will take the opamp's output (\$ V_G \$) to either rails (10V or 0V).
  5. If we start with \$ V_+ > V_- \$, then the opamp will swing to the positive rail and output 10V, and \$ V_{GS} \$ is essentially zero (\$ V_S - V_G = 10V - 10V = 0 \$). The PMOS is switched off, and \$ V_{OUT} \$ will be 0V.
  6. Following step 5, \$ V_{OUT} \$ is zero and so will \$ V_+ \$. We have now \$ V_- > V_+ \$ and opamp will swing to the negative rail which is ground, and output 0V at \$ V_G \$. Since \$ V_G \$ is more negative than \$ V_S \$ for the enhancing PMOS, the transistor conducts in the saturation mode with an effective resistance that consumes half of the supply to leave \$ V_{OUT} \$ at 5V

According to my analysis, \$ V_{OUT} \$ should fluctuate between 5V and 0V because \$ V_- \$ and \$ V_+ \$ can never be perfectly equal. But an LDO should output a stable 5V - how does it work and in which steps I had my thinking wrong?

z1

[EDIT]

Let me try to visualize @Rohat Kılıç and @tobalt's comment to see if I understand them correctly. So \$ V_{SG} \$ changes the operation point and thus changes the current \$ I_D \$. The relation between gate voltage \$ V_{SG} \$ and the drain/source current \$ I_{D} \$ is what produces the so called "variable resistor" effect. If \$ V_{OUT} \$ drops below 5V, the PMOS drives a higher \$ I_{D} \$ through \$ R_1 \$ and \$ R_2 \$ to increase the \$ V_{OUT} \$.

And vice versa: when \$ V_+ > V_- \$, opamp's output will increase positively at \$ V_G \$, causing \$ V_{SG} \$ to drop, less current \$ I_{D} \$ to the voltage divider, and output voltage to drop until it hits its regulated target of 5V.

z3

\$\endgroup\$
10
  • \$\begingroup\$ Think of the PMOS as a variable resistor controlled by the output of the opamp. And carefully read @tobalt's answer below. According to my analysis, VOUT should fluctuate between 5V and 0V this is oscillating and an indication to unstability. \$\endgroup\$ May 28 at 11:07
  • 1
    \$\begingroup\$ Remember an opamp doesn't have infinite bandwidth, it takes time to swing from rail to rail. And if on the way there it happens to pass by a point that drives the error signal to zero... \$\endgroup\$
    – hobbs
    May 28 at 11:19
  • 1
    \$\begingroup\$ The operating point of the PMOS here shifts from active (saturation) to linear (ohmic) region as VIN gets higher than VOUT (in other words, VDS increases). In the linear region, the VGS of the PMOS is kept around its threshold by the feedback network. Remember that an opamp is not a fast device that can hit its output to either rail in zero time (i.e. the slew rate), as @hobbs stated in his comment above. \$\endgroup\$ May 28 at 11:50
  • 1
    \$\begingroup\$ This question got me curious, so I just posted another one (electronics.stackexchange.com/questions/567355/…) with a comparison between NMOS and PMOS \$\endgroup\$
    – devnull
    May 28 at 13:14
  • 1
    \$\begingroup\$ Notice that in step 5 when V"+" > V"-" the opamp output voltage will start to swing to the positive rail. And this change in opamp output voltage is not instant, the voltage does not jump. The voltage will ramp up at a speed determined by the op-amp slew rate. At the same time, the Vgs voltage will decrease as well, thus the Id current must also decrease. If so, the Vout voltage will decrease too. \$\endgroup\$
    – G36
    May 28 at 20:03
3
\$\begingroup\$

According to my analysis, VOUT should fluctuate...because V− and V+ can never be perfectly equal.

Why doesn't the op-amp oscillate?

This is a very good question. But the answer is somewhat complex.

It is true that if the inputs of an op-amp differ by very much, the output will swing to one or the other rail voltage. But there is a small window, where the difference in input voltages is (more or less) linearly amplified. How large is this window?

An op-amp might have a voltage gain of around 100,000. If the supply rails differ by 10 V, then the window of differential input voltages which do not cause the output to swing to the rails is 10V/100,000 = 100 uV. That is not much.

You argued:

Any fluctuation or difference between V− and V+ will take the opamp's output (VG) to either rails (10V or 0V).

That is technically not true, the input voltages need to swing 100 uV, but intuitively, 100 uV is "so close to 0", that one would wonder whether oscillation would occur anyway.

In fact, if op-amps were "ideal" amplifiers, this small window would probably NOT be sufficient to keep the circuit from oscillating. But op-amps are not "ideal" amplifiers, but have an important component which is often not discussed -- a "compensating" capacitor.

A compensating capacitor within an op-amp acts as an "integrator" within the op-amp. A sudden change of input voltages does not cause an immediate change in the output. Rather, it causes the output to climb (or descend) at a specific rate called the maximum slew rate. In a system with feedback, this dampens rapid changes within the system. Hopefully, it allows changes to take place slowly enough that the op-amp can find a stable point within the very small window where the output is not driven to one of the rail voltages.

Is the compensating capacitor enough? Not always when op-amps are used as discrete components, and they are driving certain loads, for example capacitative loads, they may be prone to oscillation. The gate of a MOSFET is somewhat of a capacitative load (though not a huge one.) However, if an op-amp is designed specifically for a given application, for example in a integrated LDO, the op-amp designer can choose the compensating capacitor to be whatever is needed.

[Not part of your question, but you may be interested to know that the compensating capacitor is what is responsible for the 20 dB/decade roll-off of op-amp gain with frequency. That roll-off is the price paid for stability.]

\$\endgroup\$
7
\$\begingroup\$

The opamp will settle such that \$V_{gs}\$ for the PMOS is close to its threshold. The FET is almost never fully on or off unless very briefly during startup and step changes.

When Vout drops a little, so will the voltage at the IN+ of the opamp. Therefore the opamp output will drop also a little. This makes the \$V_{gs}\$ more negative, opening the PMOS a little more. That in turn rises the Vout again, compensating the initial drop.

Like any feedback control, this can become unstable if the output changes occur more rapidly then the opamp can compensate or detect them.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.