# Intuition for stability differences between PMOS and NMOS linear power supplies

Reading this question and the linked TI's LDO document led me to a more direct comparison between the two approaches:

Notes:

1. I'm using a separate V+ for the general purpose opamp to provide more head room to the positive rail and exclude PSRR from the analysis
2. The low values for the voltage divider are just to simply provide a high load current (these are ideal resistors anyway)
3. External compensations are intentionally not included, for a more direct comparison

The circuit with a PMOS is a beautiful oscillator (not even considering the overshoot here):

An AC analysis on the input voltage seems to show why:

Analyzing $$\V_{GS}\$$ in two approaches (assuming both MOSFETs in saturation -- $$\V_{DS}\$$ changes don't change source/drain current):

• with the NMOS, a +1 V step on the the input doesn't directly affect $$\V_{GS}\$$, hence the source current is not directly affected

• with the PMOS, a +1 V step on the the input directly affects $$\V_{GS}\$$, hence the source current is directly affected (increased)

• the NMOS provides a direct negative feedback for load changes ($$\V_{GS}\$$ increases with a reduction in the load resistance), which is not present with the PMOS configuration

Question: is the above reasoning correct as an intuition on why the PMOS circuit requires more attention to obtain a stable behavior?

This old question provides some interesting discussion around the "positive" feedback.

• It's an interesting question. Putting these circuits side by side just shows how similar they are. I've also wondered why the P types were more prone to oscillations. May 28 '21 at 13:35
• The nmos acts as a source follower, while the pmos act like a common source amplifier. The common source amplifier (pmos) introduces gain in the forward path.
– Mike
May 28 '21 at 13:46
• This can be analyzed many ways with Bode , Nyquist Plots and loss of phase margin by added gain. Now see how easy it is to use a PMOS LDO as an SMPS with built-in oscillator ;) by adding series inductance May 28 '21 at 14:02
• Thanks for these comments. I neglected the difference in gain despite the huge difference which is clear in the AC analysis. It certainly deserves a "bullet" (maybe the most important one) in the reasoning on why these circuits are such headaches. May 28 '21 at 14:10
• Now insert 2 resistors on the Op Amp to reduce the gain from ? 100k to 100 and see how stable it is May 28 '21 at 14:22

with the NMOS, a +1 V step on the the input doesn't directly affect VGS, hence the source current is not directly affected

Yes

with the PMOS, a +1 V step on the the input directly affects VGS, hence the source current is directly affected (increased)

Yes

the NMOS provides a direct negative feedback for load changes (VGS increases with a reduction in the load resistance), which is not present with the PMOS configuration

Er, I'm not sure what is meant by "direct", here. Perhaps this. In the NMOS circuit, the FET appears in what is essentially an source-follower configuration, which has very low small signal output impedance. In the PMOS circuit, the FET appears in what is essentially a common source configuration, which has higher small signal output impedance. If the gate voltage were kept stable in both circuits, then in the circuit with lower small signal output impedance (NMOS circuit) a change in load will cause a smaller change in voltage than in the circuit with larger small signal output impedance. If that is what you mean by "direct" feedback, then "yes".

• +1 Thanks for the improvement on the description. I'm simulating now the step response to large resistance changes in the load. May 28 '21 at 14:12
• @devnull. I've sent lots of data to you devnull. :-) May 28 '21 at 14:13