I am working to reuse some Arduino code on my Cyclone V GX FPGA using a compiler I have found on GitHub. https://github.com/dimag0g/nios_duino

I was also able to generate the HDL code for both the module and its instantiation from the SOPC builder, shown here.

Module Code:

module nios_duino (

input       clk_0_ext_clk;
input       clk_in_reset_reset_n;
input       cpu_reset_cpu_resetrequest;
output      cpu_reset_cpu_resettaken;
input       i2c_0_ext_sda_in;
input       i2c_0_ext_scl_in;
output      i2c_0_ext_sda_oe;
output      i2c_0_ext_scl_oe;
inout   [15:0]  pio_0_ext_export;
output  [12:0]  sdram_0_wire_addr;
output  [1:0]   sdram_0_wire_ba;
output      sdram_0_wire_cas_n;
output      sdram_0_wire_cke;
output      sdram_0_wire_cs_n;
inout   [15:0]  sdram_0_wire_dq;
output  [1:0]   sdram_0_wire_dqm;
output      sdram_0_wire_ras_n;
output      sdram_0_wire_we_n;
input       spi_0_ext_MISO;
output      spi_0_ext_MOSI;
output      spi_0_ext_SCLK;
output      spi_0_ext_SS_n;
input       uart_0_ext_rxd;
output      uart_0_ext_txd;

Instantiation Code:

nios_duino u0 (
    .clk_0_ext_clk              (<connected-to-clk_0_ext_clk>),              //    clk_0_ext.clk
    .clk_in_reset_reset_n       (<connected-to-clk_in_reset_reset_n>),       // clk_in_reset.reset_n
    .cpu_reset_cpu_resetrequest (<connected-to-cpu_reset_cpu_resetrequest>), //    cpu_reset.cpu_resetrequest
    .cpu_reset_cpu_resettaken   (<connected-to-cpu_reset_cpu_resettaken>),   //             .cpu_resettaken
    .i2c_0_ext_sda_in           (<connected-to-i2c_0_ext_sda_in>),           //    i2c_0_ext.sda_in
    .i2c_0_ext_scl_in           (<connected-to-i2c_0_ext_scl_in>),           //             .scl_in
    .i2c_0_ext_sda_oe           (<connected-to-i2c_0_ext_sda_oe>),           //             .sda_oe
    .i2c_0_ext_scl_oe           (<connected-to-i2c_0_ext_scl_oe>),           //             .scl_oe
    .pio_0_ext_export           (<connected-to-pio_0_ext_export>),           //    pio_0_ext.export
    .sdram_0_wire_addr          (<connected-to-sdram_0_wire_addr>),          // sdram_0_wire.addr
    .sdram_0_wire_ba            (<connected-to-sdram_0_wire_ba>),            //             .ba
    .sdram_0_wire_cas_n         (<connected-to-sdram_0_wire_cas_n>),         //             .cas_n
    .sdram_0_wire_cke           (<connected-to-sdram_0_wire_cke>),           //             .cke
    .sdram_0_wire_cs_n          (<connected-to-sdram_0_wire_cs_n>),          //             .cs_n
    .sdram_0_wire_dq            (<connected-to-sdram_0_wire_dq>),            //             .dq
    .sdram_0_wire_dqm           (<connected-to-sdram_0_wire_dqm>),           //             .dqm
    .sdram_0_wire_ras_n         (<connected-to-sdram_0_wire_ras_n>),         //             .ras_n
    .sdram_0_wire_we_n          (<connected-to-sdram_0_wire_we_n>),          //             .we_n
    .spi_0_ext_MISO             (<connected-to-spi_0_ext_MISO>),             //    spi_0_ext.MISO
    .spi_0_ext_MOSI             (<connected-to-spi_0_ext_MOSI>),             //             .MOSI
    .spi_0_ext_SCLK             (<connected-to-spi_0_ext_SCLK>),             //             .SCLK
    .spi_0_ext_SS_n             (<connected-to-spi_0_ext_SS_n>),             //             .SS_n
    .uart_0_ext_rxd             (<connected-to-uart_0_ext_rxd>),             //   uart_0_ext.rxd
    .uart_0_ext_txd             (<connected-to-uart_0_ext_txd>)              // txd

However, once I generated the SystemVerilog HDL, I always encounter this syntax error when compiling with the instantiation code as the top level entity:

Error (10170): Verilog HDL syntax error at nios_duino_inst.sv(1) near text: "("; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword.

Is there any way I can eliminate this error? I have already tried to move the terminating semicolon to other locations, checked for missing commas, and altered the spacings.

  • \$\begingroup\$ Do you have an 'include in nios_duino_inst.sv.? Looks like the error message says that the error is on line 1. So maybe the error is in the included file. You should include the entire file, not just a screen shot. \$\endgroup\$
    – IanJ
    May 29, 2021 at 14:37

1 Answer 1


I am going to assume that the files in question were generated automatically by Quartus from Platform Designer (based on the link you provide which contains a .qsys file).

The auto generated files include a number of "template" and "black-box" files. These files, including ones which end with _inst.(sv|v|vhd) are not intended to be compiled - they are not valid Verilog or VHDL syntax. They are intended to be copied and pasted into your own module and modified as required.

The syntax error on line 1 is because the _inst.sv file doesn't begin with the keyword module, it starts with the name of the module to be instantiated. This is not valid SystemVerilog syntax. Again, because it is not meant to be, it is a template.

Similarly, the file name _bb.sv which I'm guessing is the "module code" as you describe it is also not intended to be compiled. It is a black box file. All that is contained in the black box file is the list of ports, and directions, nothing more.

Again, assuming Platform Designer, your actual IP files will be inside the synthesis and/or simulation folder in the same directory as the templates. Inside these folders you will find a .qip (synthesis file list) or .sip (simulation file list) which should be included in your Quartus project.

In addition you will find a .sv or .v file with the same name as the .qip file which should also be included in your Quartus project. This .sv file is the actual module which the instantiation template shows you how to instantiate. If you have no further connections you need to make, you can use this file as the top level module in your project.


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