I have a question about the stage inside an opamp where the differential input is converted to single ended output.


simulate this circuit – Schematic created using CircuitLab

1)In order for Q3 to mirror the current in Q4 both Q3 and Q4 must operate at the linear(forward active)region .How is that even possible?(I mean Q1 and Q2 must operate at the linear region). 2)How does the voltage Vo depend on the difference between Vin1 and Vin2?


In order for Q3 to mirror the current in Q4 both Q3 and Q4 must operate at the linear(forward active)region How is that even possible?

Correct, Q3 and Q4 must operate in active mode. Q3 will be in active mode as it is connected as a "diode". Then Vce = Vbe and the transistor must therefore be in active mode.

Q4 will be in active mode as long as it has a Vce that is large enough.

As long as the output voltage is limited and Vcc is large enough, that will not be an issue.

Note that the output of this circuit is actually a current output so you should be terminate it with a load, usually a resistor. That will limit the output voltage swing.

Without a load, the output current (Ic,Q3 - Ic,Q2) has "nowhere to go" and that means that the output voltage will vare a lot.

I suggest that you put this circuit in a simulator like LTSpice and see how it behaves.


This is just a very high current gain frontend with no load or feedback to regulate the DC output and the output resistance to convert voltage to current and thus voltage gain.

The common mode Bias current is defined by Vb1 and Vb2 and thus the emitter load Ve/Ie. so the DC must be near equal and then a load on Vo to get a thing any AC without being saturated or turned off by the differential input.

So this front end can have excessive voltage gain with a current source load, unless regulated by feedback with further stages with high current gain and thus convert high impedance to load impedance in further stages, so that Vo can be regulated in the mid-scale linear region somehow. It is not necessary now to explain how, just assume the collector load Rc must be regulated somehow to keep in the linear range to ensure that for a limited common mode DC bias input range that the single ended output is balanced using differential balance current feedback.


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