I am trying to place multiple ring oscillators using XDC macros. I have been able to follow the steps on the video by Xilinx on XDC macros and it worked.

However, I am facing errors and critical warnings when I am trying to run implementation even though the synthesis was successful. I don't know how to solve them. I have 3 modules, one is the top module and the other two are the Ring oscillator and ring counter module.

Below are the error messages:

[DRC MDRV-1] Multiple Driver Nets: Net u4/w14 has multiple drivers: u4/w14_inferred_i_1/O, u1/w14_inferred_i_1/O, u2/w14_inferred_i_1/O, u3/w14_inferred_i_1/O, and w14_inferred_i_1/O.
[Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.
**Critical warnings:**
[Synth 8-6859] multi-driven net on pin w14_inferred_i_1_n_0 with 1st driver pin 'u1/w14_inferred_i_1/O' .
[Synth 8-6859] multi-driven net on pin w14_inferred_i_1_n_0 with 2nd driver pin 'w14_inferred_i_1/O'
[Synth 8-6859] multi-driven net on pin w14_inferred_i_1_n_0 with 3rd driver pin 'u2/w14_inferred_i_1/O'
[Synth 8-6859] multi-driven net on pin w14_inferred_i_1_n_0 with 4th driver pin 'u3/w14_inferred_i_1/O'
[Synth 8-6859] multi-driven net on pin w14_inferred_i_1_n_0 with 5th driver pin 'u4/w14_inferred_i_1/O'

Below is the code where I call 5 Ring oscillators in the top module:

`timescale 1ns / 1ps

module top(countreset,reset,en,enable,count,out2,clk);

input countreset;
input reset;
input en;
input enable;
input clk;

//output [31:0] count;
output [15:0] count;
output out2;

ila_0 debugger(

ring_osc u0(.enable(enable)
, .out(out2));

ring_osc u1(.enable(enable)
, .out(out2));

ring_osc u2(.enable(enable)
, .out(out2));

ring_osc u3(.enable(enable)
, .out(out2));

ring_osc u4(.enable(enable)
, .out(out2));

ro_counter fgh(.reset(reset),
.countrest(countreset) ,
.ena(en) ,


Below is the schematic if this helps.

enter image description here


1 Answer 1


Well, the error messages are very clear: You're driving the same output signal with multiple drivers. And that's exactly what your code (and schematic) show: you're driving out2 with several ring oscillators. Obviously, that's not "proper" digital design, so the synthesizer stops you from doing that.

It's not clear what your intention there is – it makes no sense to drive the same line with multiple ring oscillators.

Also, fair warning: by definition of what a ring oscillator is, it's a metastable component, and not only might you get warnings about that, it's even possible that Vivado will completely get rid of it and fix its output value. I haven't done that for Vivado, but I do remember that you needed pretty ugly hacks to convince other synthesizers/technology mappers that what you want to do is "legal" enough to become a configuration bitstream. Strictly speaking, ring oscillators aren't "digital" components, as their behaviour is not founded in discrete-time description, so anything that checks a design for validity will notice they are impossible to implement safely.


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