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When I use ISim of ISE14.7 to simulate a DSP48A1-based multiplier, the DSP output signal (dsp_o) of the sequence diagram always starts with many '0' outputs. This results in the loss of some of the initial product results.

My code and sequence diagram are as follows.

module tb_dsp();

    reg clk;
    reg rst;
    wire [27:0] dsp_o;
    
    reg [12:0] a_i = 3;
    reg [12:0] b_i = 3;

    initial begin
        clk = 0;
        #5
        forever
            #5
            clk = ~clk;
    end
    
    initial begin
        rst = 0;
          #10
          rst = 1;
          #40
          rst = 0;
        #16000 
        $stop;
    end
    
    always @(posedge clk) begin
        a_i <= a_i+1;
        b_i <= b_i+1;
    end

     MULT_MACRO #(
      .DEVICE("SPARTAN6"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6" 
      .LATENCY(3),        // Desired clock cycle latency, 0-4
      .WIDTH_A(14),       // Multiplier A-input bus width, 1-18
      .WIDTH_B(14)        // Multiplier B-input bus width, 1-18
   ) MULT_MACRO_inst (
      .P(dsp_o),     // Multiplier output bus, width determined by WIDTH_P parameter 
      .A({1'b0,a_i}),     // Multiplier input A bus, width determined by WIDTH_A parameter 
      .B({1'b0,b_i}),     // Multiplier input B bus, width determined by WIDTH_B parameter 
      .CE(1'b1),   // 1-bit active high input clock enable
      .CLK(clk), // 1-bit positive edge clock input
      .RST(rst)  // 1-bit input active high reset
   );
    
endmodule

Sequence diagram

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1 Answer 1

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the sequence diagram always starts with many '0' outputs.

It is because, the Multiplier block you use is a pipelined design to increase the throughput. Every pipelined design has an initial latency, after which you get the outputs every clock cycle.

The latency is what you have configured during the instantiation:

.LATENCY(3),        

As you can see the output for 12 x 12 @90ns appeared after 3 clock cycles as 144 @120ns.

The output for 13x13 @100ns appeared as 169 @130ns, and so on................

If you don't want this latency, you can configure it to lower value (I guess 0 is also supported, in that case it will be a purely combinational logic). But lowering it will affect the timing performance of the core as it removes the fifo/register stages between the pipeline stages, thereby reducing the maximum achievable frequency of operation and hence throughput.


Sidenote:

Curious how the reset was pulled down @50 ns but the outputs for the inputs from 50 ns i.e., 8, 9, 10, 11 never appeared at the outputs. It is probably because of the global reset mechanism. See this extract from page 13 of Synthesis Guide UG-900

Apply stimulus data after 100 ns to account for the default Global Set/Reset (GSR) pulse used in functional and timing-based simulation.

So maybe that's why your stimuli before 100 ns were not sampled, as it was in reset state.

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