Electrical model of ADG436 switch

Question

I need some help with understanding the electrical model of ADG436. After reviewing the datasheet, I am still unsure if my simplified schematic for this part is correct. I used the values for +/- 15V supply from the datasheet: Ron 12Ohm, Cs(off) 13p, Cs(on) 49p, Cd 49p. The main doubt is Cs_off and Cs_on notation. My understanding is that C_on is a parasitic capacitance while the channel is on and C_off is a parasitic capacitance while the channel is off both in respect to GND.

Therefore, depending on control lines, one channel will conduct by providing a low impedance path (12 Ohm) and this channel would also exhibit a parasitic capacitance of 49pF to GND.

Could someone verify my assumption and schematic attached?

Answer 1

The above model is a good simplified model and will work for a 'worst case' resistance model in some cases. If you need a more detailed model consider using the full spice model (parts->switches->ADG436)

Also make sure that you are using the right resistance, as the resistance changes on temperature (and drain/source voltage). If the signal on the terminal is -15V and the temperature is 25C then the resistance would be ~13Ω

Source: https://www.analog.com/media/en/technical-documentation/data-sheets/ADG436.pdf

Answer 2

If your main interest is the capacitance:

• you need only one 46 pF caps for the on channel.
• the capacitance is not to ground but in part to v+,in part to V- and in part in parallel with the channel resistance. This goes for every capacitance value in the datasheet.

Each analog pin of the device faces both an NMOS and PMOS transistor. The body of NMOS is connected to V- and the body of PMOS is connected to V+. But as the two transistors have different sizes, the capacitance to v+ and v- is not exactly equal.

The reason why the drain pin has more capacitance is because it is connected to two channels