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See: https://www.quora.com/Why-is-peak-inverse-voltage-2Vp-in-a-half-way-rectifier-with-a-capacitor-filter

It makes sense to me that the PIV occurs at the bottom of the negative half cycle for the rectifier without the filter. What doesn't make sense to me is why the PIV for the rectifier with the filter occurs at the top of the positive half cycle. It seems like the reverse voltage is equal to the capacitor voltage minus the supply voltage, and at the top of the positive half cycle that would be zero. Am I missing something here?

Edit:

output waveform

This image from the above link is what's confusing me. The above answers state that PIV is 2Vp because the voltage from the capacitor and the maximum negative voltage from the source are equal in magnitude and across the diode at the same time. However, this diagram shows the capacitor voltage is only equal in magnitude to Vp at the same peaks as the waveform without the capacitor (the top of the positive half cycle).

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  • \$\begingroup\$ Please edit your question to quote (use > markdown) the part of that long series of posts that is causing your confusion. \$\endgroup\$
    – Transistor
    Jun 4, 2021 at 6:38
  • \$\begingroup\$ Please draw a diagram. Based on what you say, there is some misconception maybe, as if diode charges a capacitor to say +10V on positive cycle, PIV does not happen on positive cycle peak as there is 0V difference, but PIV happens on negative cycle peak when sine wave is -10V but capacitor has +10V so there is 20V over diode. \$\endgroup\$
    – Justme
    Jun 4, 2021 at 6:39
  • \$\begingroup\$ ... the PIV for the rectifier with the filter occurs at the top of the positive half cycle. no, it doesn't. \$\endgroup\$ Jun 4, 2021 at 6:43
  • \$\begingroup\$ @Justme Okay that makes more sense but doesn't the capacitor start discharging before the negative cycle peak? So PIV would be less than 2Vp. \$\endgroup\$ Jun 4, 2021 at 6:53
  • \$\begingroup\$ The capacitor would be discharging slowly (as shown in the lower diagram,) but would initially be at Vp. The value of the load resistance and the value of the capacitor would determine the actual discharge time, (if these values were known a more exact calculation could be made). But since these values are not given you might assume that the worse case (max PIV) is with a high load resistance and a large value capacitor. \$\endgroup\$
    – Nedd
    Jun 4, 2021 at 7:30

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I believe that the second explanation "is" trying to say that the higher PIV (2Vp) is seen during the negative cycle. Perhaps the explanation could have been more clear if it were written as:

"Here, the capacitor is connected across the load. During the positive half cycle of input voltage, the capacitor charges to Vp. At the next negative half cycle of input voltage (before the capacitor can discharge), the diode becomes reverse biased, the diode then sees Vp at the cathode (capacitor side) and -Vp at the anode side."

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