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I'm designing a 4 layer PCB (Signal-GND-PWR-Signal) that has power input and motor connectors placed as seen in the picture. In order to avoid thick traces I traced a power path around the PCB composed of thinner tracks like in the picture on every layer and stitched them with vias.

enter image description here

My question is, would such design raise any EMI/SI issues? I'm concerned because it resembles a faraday cage except not wired to ground so I wonder if it would increase EMI rather than reducing it. I also would like to ask if the design would be better without the vias.

Thank you.

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    \$\begingroup\$ What's wrong with power plane? \$\endgroup\$
    – bobflux
    Jun 4 at 21:20
  • \$\begingroup\$ Oh, sorry for forgetting to mention, I have a power plane too but that's for VCC (3.3V). This power path however is to feed motors directly from the source. \$\endgroup\$
    – afkrmc
    Jun 5 at 19:30
  • \$\begingroup\$ How many amps for the motors? \$\endgroup\$
    – bobflux
    Jun 5 at 19:34
  • \$\begingroup\$ The motors can draw up to 4A. \$\endgroup\$
    – afkrmc
    Jun 5 at 20:17
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You have made a nice loop antenna, whether it becomes a problem will be determined by the currents on the antenna. Because the currents will enter at one connector and go both ways around to the 'exit connector' it may not be a problem. The vias probably don't make a much of a difference.

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  • \$\begingroup\$ Would breaking the loop by removing the track between J3 and J4 help? \$\endgroup\$
    – afkrmc
    Jun 5 at 19:34
  • \$\begingroup\$ You still have a loop antenna (its the geometry that counts) and then all the currents will go in one direction. The worst case would be the two farthest apart connectors. You could actually calculate the magnetic field with the currents (if you know the currents) and see if its a problem \$\endgroup\$
    – Voltage Spike
    Jun 6 at 4:22
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Based on this video, yes it will create a EMI issue, since there is not GND under (or over) the VCC/power traces.

This will cause the return currents (if the VCC/power has ripple and its not pure DC) to "go around" to connect with the GND, like this:

22:12 of the video

fields pcb

The more you put GND under your traces and Power lines, the better the EMI.

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  • \$\begingroup\$ Would keeping the traces in the inner layers reduce EMI? \$\endgroup\$
    – afkrmc
    Jun 5 at 20:19
  • \$\begingroup\$ Your answer depends on the kind of circuit. Will there be both analog and digital circuits on the same pcb? What frequency does it operate to? (the mcu/cpu?). How many layers do you have/need? If you watch the video, you will understand: outer layers emit more noise since they dont have a GND plane on top of them. \$\endgroup\$ Jun 5 at 23:01

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