0
\$\begingroup\$

Would a sinewave be a suitable input for the CD4046? I am trying use the CD4046 as a phase locked loop for a lock-in amplifier (the output from the CD4046 will be multiplied with a signal.) I have a sinewave for the reference (the signal is modulated with the same frequency as the reference) and was unsure if this would be suitable for the CD4046. It appears the IC has two phase comparator, one using exclusive-or network while the other edge controlled memory network. The exclusive-or network appears to require a square wave of 50% duty cycle however I am unsure if the second phase comparator would work with a sinewave as all examples I could find use square waves.

CD4046 datasheet

\$\endgroup\$
1
  • \$\begingroup\$ For lock-ins, you most likely need to vary the phase relationship between the PLL's sine-wave input, and its square wave VCO output. XOR phase comparator does allow a phase shift. while the edge-controlled phase comparator does not. You may want to include a phase-shifting circuit external to the 4046, especially if you use its edge-controlled phase comparator. \$\endgroup\$
    – glen_geek
    Jun 5, 2021 at 14:28

2 Answers 2

3
\$\begingroup\$

The CD4046 phase comparators require a CMOS-level digital input.

If you convert the sine wave to a digital signal using a comparator you can use that signal.

Under some specific conditions you might be able to use a sine wave directly but it would not be ideal. The voltage levels would have to be strictly within the power supply rails by 300mV or so, and be large enough to meet Vih and Vil limits and the frequency would have to be high enough to meet the maximum rise and fall times shown on the datasheet.

\$\endgroup\$
0
\$\begingroup\$

The datasheet plot Fig 14? show the method to feed AC coupling sine wave inputs using Vdd/2 bias. You can fine tune this for a fixed circuit conditions but the duty cycle error must be taken into account for the error on input threshold. It shows the amplitude varying from 0.8Vp for Vdd=5V at 1MHz going down to the left with lower f input. This would be temperature sensitive for threshold drift. You can easily adjust phase externally with a variable one shot or slightly with bias to the VCO to inject a phase error equivalent current.

But doesn’t a lock-in amp have its own PLL?

\$\endgroup\$
3
  • \$\begingroup\$ I thought a lock-in amplifiers consist of a multiplier that would multiply the signal with a reference which would then be passed through a low pass filter. The reference could come from a PLL but is not necessarily a part of the lock-in amp? I am not quite sure what Fig14 is demonstrating so I will have a further look into that. I also would like to avoid using variable phase shifters which I believe you are recommending? \$\endgroup\$
    – Sank
    Jun 5, 2021 at 15:45
  • \$\begingroup\$ You can regenerate a PLL clock that is more than the incoming signal, if you have s \$\endgroup\$ Jun 5, 2021 at 17:11
  • \$\begingroup\$ You can generate a clock which is more stable than the incoming signal if you have specs or at any frequency multiple using logic dividers with any PLL \$\endgroup\$ Jun 5, 2021 at 17:12

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.