I have a code mult.vhd that should assign '0' on some locations of three arrays called "c", "mult" and "sum". Nonetheless the assignments on the corresponding locations of those 3 arrays only work with the array called "c". Each assignment on the arrays "mult" and "sum" leaves the corresponding location with "U" value, that means the array values do not change after running the corresponding assignment sentence.
Does anyone know why the assignments on the arrays "mult" and "sum" do not work?
I have a file called test_bench.vhd. Find as follows the code of mult.vhd:
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06/01/2021 09:33:03 PM
-- Design Name:
-- Module Name: mult - structure
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mult is
port (a: in std_logic_vector (4 downto 0);
b: in std_logic_vector (4 downto 0);
result : out std_logic_vector (9 downto 0));
end mult;
architecture structure of mult is
type t_matrix is array (0 to 5-1, 5*2-2 downto 0) of std_logic;
constant zero : std_logic := '0';
signal c, sum , mul : t_matrix;
signal caca: std_logic;
begin
p_set_zeros: process
begin
---------------------carry=zero
c(0,0)<=zero;
loop_carry_1_to_size: for j1 in 5 to 5*2-2 loop
c(0,j1)<=zero;
end loop loop_carry_1_to_size;
loop_rigt_bottom_triangle_c: for i2 in 1 to 5-2 loop
for j2 in 0 to i2 loop
c(i2,j2)<=zero;
end loop;
end loop loop_rigt_bottom_triangle_c;
c(5-1,0)<=zero;
---------------------mul=zero
right_bottom_corner_mul_1: for i3 in 0 to 5-2 loop
right_bottom_corner_mul_2: for j3 in 0 to i3 loop
mul(i3,j3)<=zero;
end loop right_bottom_corner_mul_2;
end loop right_bottom_corner_mul_1;
mul(5-1,0)<=zero;
left_top_corner_mul_1: for i4 in 0 to (5-3) loop
left_top_corner_mul_2: for j4 in 5+i4+1 to 5*2-2 loop
mul(i4,j4)<=zero;
end loop left_top_corner_mul_2;
end loop left_top_corner_mul_1;
---------------sum=zero
loop_first_row_zeros: for j5 in 5 to ((5)*2-2) loop
sum(0,j5)<=zero;
end loop loop_first_row_zeros;
caca<='1';
wait;
end process p_set_zeros;
p_multiplications : process (a, b)
--variable v_producto : t_pp := (( others => (others => ’0’)));
begin -- process multiplications
for i6 in 0 to 5-2 loop
for j6 in 0 to 4 loop
if i6 = 0 then
sum(i6, j6) <= a(i6) and b(j6);
end if;
mul(i6, j6+i6+1) <= a(i6+1) and b(j6);
end loop; -- j
end loop; -- i
end process p_multiplications ;
end structure;
Find as follows the code of test_bench.vhd:
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06/02/2021 01:47:53 PM
-- Design Name:
-- Module Name: test_bench - structure
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test_bench is
end test_bench;
architecture structure of test_bench is
COMPONENT mult
port (a: in std_logic_vector (4 downto 0);
b: in std_logic_vector (4 downto 0);
result : out std_logic_vector (9 downto 0));
end COMPONENT;
signal a, b: std_logic_vector(4 downto 0);
signal result: std_logic_vector(9 downto 0);
begin
i_mult: mult port map(a,b,result);
p_input: process
begin
a<="00100";
b<="01000";
wait for 25 ns;
a<="00011";
b<="11000";
wait for 25 ns;
a<="00111";
b<="00011";
wait for 25 ns;
a<="00110";
b<="01000";
wait for 25 ns;
a<="01001";
b<="00001";
wait for 25 ns;
a<="10010";
b<="01000";
wait for 25 ns;
a<="10011";
b<="00010";
wait for 25 ns;
a<="10000";
b<="00100";
wait for 25 ns;
a<="00010";
b<="11000";
wait for 25 ns;
a<="00001";
b<="10000";
wait for 25 ns;
a<="00100";
b<="00010";
wait for 25 ns;
a<="00010";
b<="00010";
wait for 25 ns;
a<="00110";
b<="00111";
wait for 25 ns;
a<="00011";
b<="00011";
wait for 25 ns;
a<="01001";
b<="01010";
wait for 25 ns;
a<="00110";
b<="10101";
wait for 25 ns;
a<="11010";
b<="00111";
wait for 25 ns;
a<="11010";
b<="11010";
wait;
end process p_input;
end structure;
```
