I created two always blocks in Verilog. In one always block, one bit register variable is flipping and in other always block, a counter variable is running. Now when counter will reach to a specific value I want to read the status of another loop variable. But couldn't understand the correct way to do it. Please help. Thank you for your time.

Verilog code:

module test1(
    input enb,
    input shift,
    input customClk,
    output out,
    output intr,
    input reset

reg [31:0] counter;
reg temp_out;
reg intr;
reg out;

always @ (posedge reset) begin
    counter <= 32'b0;
    temp_out <= 1'b0;
    intr <= 1'b0;

always @ (posedge customClk) begin
    counter <= counter + 1'b1;
    if(counter==5000) begin
        counter <= 32'b0;
        out = temp_out;
        intr = 1'b1;

always @ (*) begin
    temp_out <= ~temp_out;


Testbench code:

module test1_tb;

    // Inputs
    reg enb;
    reg shift;
    reg customClk;
    reg out;
    reg intr;
    reg reset;

    // Instantiate the Unit Under Test (UUT)
    test1 uut (

    initial begin
        // Initialize Inputs
        enb = 0;
        shift = 0;
        customClk = 0;

        // Wait 100 ns for global reset to finish
        reset =1;
      if(intr) begin
    always #5 customClk = ~customClk;

Simulation output:

ISim Output

  • \$\begingroup\$ So why did you comment // out = temp_out. Isn't that what you want \$\endgroup\$
    – Mitu Raj
    Jun 7, 2021 at 5:43
  • \$\begingroup\$ Actually I will print the output there but I am receiving impedance in simulation for the output registers like "intr". Also out = temp_out; showing error but if i give assign out = temp_out; then I will not be able to control specific instance. What should I need to change in code. Thank you \$\endgroup\$ Jun 7, 2021 at 6:43
  • \$\begingroup\$ @DipnarayanDas if a central part of your code can't be synthesized, shouldn't that raise a red flag that you need to fix that first? \$\endgroup\$ Jun 7, 2021 at 7:00
  • 2
    \$\begingroup\$ In the Verilog code, shouldn't that be reg [31:0] counter; otherwise it is 1-bit wide \$\endgroup\$
    – Martin
    Jun 7, 2021 at 8:48
  • \$\begingroup\$ Good catch by Martin. Didn't notice that. By the way were you able to sort out? @DipnarayanDas \$\endgroup\$
    – Mitu Raj
    Jun 8, 2021 at 5:28

1 Answer 1


Your code doesn't follow the general coding guidelines, for example:

  1. You are using blocking assignments for registers inside the clocked always @(posedge ..) block. It has to be non-blocking assignment like for eg: counter <= 32'b0 ;

  2. You have a combinational loop in the combinational always @(*) block, which has undefined behaviour. Shouldn't you use a clocked always @(posedge ..) block there as well, if you are toggling the bit temp_out?

  3. The output port out is currently of wire type by default. You have to explicitly mention it as reg if you intended to drive it inside the always block and read temp_out like: out <= temp_out ;

  4. Initial blocks are used only on test benches, not on designs. They are not generally synthesisable by ASIC/FPGA tools. Use a reset signal instead to initialize registers.


Declaration of count looks wrong. It should be reg [31 : 0] count.

  • \$\begingroup\$ Hello, I want the undefined behavior. When the counter will reach at specific value, I want to get random status from that flipping bit. Kindly let me know where I am going wrong. Thank you. \$\endgroup\$ Jun 8, 2021 at 15:40
  • \$\begingroup\$ Randomisation? That should be asked as a different question as it deviates from the intention of your current question. You asked what was the error in reading temp_out in the first always block...I have answered. Hope this answer helped. \$\endgroup\$
    – Mitu Raj
    Jun 8, 2021 at 16:29
  • 1
    \$\begingroup\$ Yes definitely. The answer was really helped. I will post another question with the randomness query. Can you please identify where I am going wrong, that's why getting impedance in output? Thank you \$\endgroup\$ Jun 9, 2021 at 3:15

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