Capture register value at specific instance in Verilog

Question

I created two always blocks in Verilog. In one always block, one bit register variable is flipping and in other always block, a counter variable is running. Now when counter will reach to a specific value I want to read the status of another loop variable. But couldn't understand the correct way to do it. Please help. Thank you for your time.

Verilog code:

module test1(
    input enb,
    input shift,
    input customClk,
    output out,
    output intr,
    input reset
);

reg [31:0] counter;
reg temp_out;
reg intr;
reg out;

always @ (posedge reset) begin
    counter <= 32'b0;
    temp_out <= 1'b0;
    intr <= 1'b0;
end

always @ (posedge customClk) begin
    counter <= counter + 1'b1;
    if(counter==5000) begin
        counter <= 32'b0;
        out = temp_out;
        intr = 1'b1;
    end
end

always @ (*) begin
    temp_out <= ~temp_out;
end

endmodule

Testbench code:

module test1_tb;

    // Inputs
    reg enb;
    reg shift;
    reg customClk;
    reg out;
    reg intr;
    reg reset;

    // Instantiate the Unit Under Test (UUT)
    test1 uut (
        .enb(enb), 
        .shift(shift), 
        .customClk(customClk),
        .out(out),
        .intr(intr),
        .reset(reset)
    );

    initial begin
        // Initialize Inputs
        enb = 0;
        shift = 0;
        customClk = 0;
        reset=0;

        // Wait 100 ns for global reset to finish
        #100;
        
        reset =1;
        
      if(intr) begin
            $display("%b",out);
        end
        
    end
    
    always #5 customClk = ~customClk;
      
endmodule

Simulation output:

Answer 1

Your code doesn't follow the general coding guidelines, for example:

1. You are using blocking assignments for registers inside the clocked always @(posedge ..) block. It has to be non-blocking assignment like for eg: counter <= 32'b0 ;

2. You have a combinational loop in the combinational always @(*) block, which has undefined behaviour. Shouldn't you use a clocked always @(posedge ..) block there as well, if you are toggling the bit temp_out?

3. The output port out is currently of wire type by default. You have to explicitly mention it as reg if you intended to drive it inside the always block and read temp_out like: out <= temp_out ;

4. Initial blocks are used only on test benches, not on designs. They are not generally synthesisable by ASIC/FPGA tools. Use a reset signal instead to initialize registers.

UPDATE:

Declaration of count looks wrong. It should be reg [31 : 0] count.