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I keep getting faults on a a new batch of ESC boards based on the TI DRV8353RH & Infineon IPT020N10N3ATMA1. Please consider:

When starting a motor at 48V - 56V the DRV asserts a fault after sending a very brief PWM to the windings. Sometimes the motor buzzes for a second or so before the fault occurs. Sometimes it starts turning.

No faults occur when starting the motor at 30V. If motor is started at 30V and the VM increases to 48V or 56V no errors occur either. Also, when the DRV works, it works as expected.

The fault only resets after toggling the EN pin. Does this mean it's either VDS overcurrent, VSense overcurrent or Gate Drive Fault? We cannot find the issue.

Schematic:

enter image description here

Used variant of the schamtic (IDrive is changed to 450mA src & 450mA snk on the board): enter image description here

Half-bridge (IPT020N10N3ATMA1 FET is used, not the one on the schamtic and the RCD-clamp values are changed to 330R and 22nF): enter image description here

A correlation between the hi-side gate to gnd voltage (green), the source voltage (purple) and the fault pin (blue): enter image description here

Another PWM-rising edge on the same PCB, same MOSFET, same everything: enter image description here

It's very difficult to say when the "faulty" PWM-period occurs, this seems very random. Other phases do not display this issue. Also, the performance is very motor-specific. Some motors trigger the fault instantly, others just work.

A capture of phase B hi-side FET VS (purple), VD (green) and DRV nFAULT (blue):

nFAULT triggered on a later PWM-period nFAULT triggered on a later PWM-period

nFAULT triggered on seemingly the first PWM-period nFAULT triggered on seemingly the first PWM-period

Waveforms look similar on all half-bridges.

A capture of phase B hi-side FET VS (purple), VD (green) and DRV nFAULT (blue) at 20ns and 100ns :

20ns high side gate phase B 20ns

enter image description here 100ns

enter image description here A 20ns/div rising edge capture of the source voltage (green) and the drain voltage (purple) at 24V of phase A triggered on the VS rising edge

enter image description here A 20ns/div rising edge capture of the source voltage (green) and the drain voltage (purple) at 48V of phase A triggered on the VS rising edge

enter image description here A 20ns/div rising edge capture of the source voltage (green) and the drain voltage (purple) at 24V of phase B triggered on the VS rising edge

enter image description here A 20ns/div capture of a rising edge of the source voltage (green) and the drain voltage (purple) at 48V of phase B triggered on the VS rising edge

enter image description here A 20ns/div rising edge capture of the source voltage (green) and the drain voltage (purple) at 24V of phase C triggered on the VS rising edge

enter image description here A 20ns/div rising edge capture of the source voltage (green) and the drain voltage (purple) at 48V of phase C triggered on the VS rising edge

enter image description here A 20ns/div rising edge capture of the source voltage (green), the drain voltage (purple) and CPH at 48V of phase C triggered on the VS rising edge

MOSFET drain-areas on the top-layer:

enter image description here

MOSFET drain and source areas and DRV cooiling areas on inner 1: enter image description here

MOSFET drain and source areas on the inner 2: enter image description here This is the gnd-layer and my most controversial decision. I needed to increase the cooling areas underneath the FETS. Signals and waveforms look fine despite this.

The layout of the half-bridges on the bottom layer: enter image description here

The layout of the DRV8353RH on the bottom layer: enter image description here

A 3D-view as reference: enter image description here

The half-bridge layout of a previous, working, HW version:

enter image description here

The DRV layout of a previous, working, HW version:

enter image description here

3D-view of the previous, working, HW-revision as reference:

enter image description here

I really don't know where to look anymore. Please don't hesitate to ask for a specific capture if that would make it easier to help. I have a ton saved and could capture many more, I just did not want to clutter the post in advance.

Thanks!

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    – SamGibson ♦
    Jun 10, 2021 at 11:25
  • \$\begingroup\$ Since comments are not for extended discussion; this conversation has been moved to chat. \$\endgroup\$
    – SamGibson ♦
    Jun 10, 2021 at 11:26

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