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I am trying to implement a delay mechanism out of passive components. The digital input in this case is a PIC input pin. The operation is as follows. The capacitor is pre-charged to 5v, and then the power to the rest of the system is turned on. With the charged capacitor connected to the gate of the SCR, the SCR starts conductions, which in turn allows the transistor to conduct and sink the digital input to ground. Over time, the capacitor will discharge through R to the point where the SCR turns off, and this subsequently closes the transistor and the uC detects this to perform some action.

When R = 100kohm, it takes about 6 minutes for the cap to discharge and all the other stuff in the micro to start. When R = 120kohm, the cap does not discharge at all. Or at least it does not discharge any visible amount in 30minutes when viewed on a scope.

What is going on here? Why is it with a reasonably small change in resistance, suddenly the cap has stopped discharging?

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You are getting current thru the SCR gate. The whole circuit seems a bit silly. This should work:

Adjust C1 and R2 for the desired delay.

Added:

This was added in response to a request for clarification in a comment.

SW1 is only to show some means of charging the capacitor to Vdd. The point of the circuit is what happens when SW1 is opened. Let's say Vdd is 5 V. When SW1 opens, C1 is charged to 5V. This puts current thru the base of Q1 via R2. Let's say the B-E drop is about 500 mV. This is lower than the usual of 600-700 mV because of the very low current. That leaves 4.5 V accross R2 at T=0, which puts 4.5 µA thru the base of Q1. Let's say Q1 can be counted on to have a gain of 50. That means it can support collector current up to 4.5µA * 50 = 225µA. That would be 10.6 V accross R1, which is more than available, so Q1 saturates and the PIC input is driven low.

Since the B-E junction is assumed to be a fixed voltage, we have a simple R-C decay between C1 and R2. C1 is initially charged to 5 V and will decay to 500 mV according to our assumption of B-E looking like a fixed voltage source. That's not exact, but good enough to get a rough idea what will happen. There are other far greater uncertainties as we will see shortly. So, the C1 voltage will decay exponentially from 5 V to 500 mV. The base current will likewise decay from 4.5 µA to 0. The time constant is R*C, which is 1000 seconds. Note that even a µA or two of leakage on C1 will change this value significantly. If you can find a leakage spec, it will be a maximum, so the leakage can be anywhere from that value down to 0. The capacitor leakage therefore represents a significant uncertanty on the decay time. Let's continue with the 4.5 µA to 0 with a time constant of 1000 seconds values to show how to calculate what happens in the reset of the circuit.

Let's say this PIC input requires the voltage to be below .2 Vdd for a guaranteed logic low level. That is 1 V in this example. Let's also say the PIC pin is rated for 1 µA maximum leakage. When the PIC pin is at 1 V, there is 4 V accross R1, which means it will source 85 µA. We can now see the PIC pin leakage is insignificant with the chosen value of R1. We'll add it anyway to find that Q1 must sink 85 µA to keep the PIC pin in the guaranteed logic low state. We said before we will assume Q1 can be counted on to have a gain of 50, so that means it needs 1.7 µA of base current to guarantee a logic low output. That is .383 of the starting value, which is .96 time constants, or 960 seconds. Therefore, given all the assumptions, the PIC input will be held low for at least 960 seconds (16 minutes) after SW1 is opened.

In reality, a 1 mF cap will be electrolytic, so will have significant leakage compared to the 4.5 µA initial discharge current. This will shorten the time. Such long times are difficult with analog electronics because you need a combination of high capacitance and low leakage, which are at odds with each other in the real world.

That was the minimum time calculation. Even if C1 were a perfect capacitor, a very significant source of error comes from the uncertainty of the gain of Q1. We used 50 minimum as example. That may be a reasonable minimum over much of a 2N4401 operating range, but these things are rarely specified at such low currents. The minimum could be lower, but the maximum gain of a transistor can often be many times more than its minimum. It is the unpredictable gain of Q1 that makes the delay of this circuit unpredictable over a wide range.

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  • \$\begingroup\$ Can you maybe offer a little explanation, beyond the circuit is silly? I'm getting current through the scr gate and...? \$\endgroup\$ – Michael Feb 3 '13 at 23:31
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    \$\begingroup\$ The original circuit is silly because it uses one more resistor and an SRC compared to this circuit. Also, the digital input is being driven with an TTL-style open collector that is probably not appropriate for your device, which likely has a CMOS input which responds to voltage levels and doesn't source or sink much current. The input in your circuit has to source current when the transistor is turned on. It is not clear what the voltage is: it depends on how much current flows across the collector resistor and any additional voltage drop in the input itself. \$\endgroup\$ – Kaz Feb 4 '13 at 1:43

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