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In FPGA projects, the files are usually named after the entity they contain. I am trying to figure out these things:

  1. Is it a good practice to have multiple entities in same file?
  2. What if entity and architecture are to be kept in different files? What should the files be named in that case?
  3. Can there be multiple files or entities that have same name where the ports of the entity can be different? Is this acceptable for simulation and synthesis purpose?
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  • \$\begingroup\$ All of these are valid VHDL. Except possibly multiple files with same name, unless in different folders and compiled into different libraries. What is acceptable and good practice depends on your project's requirements and your company's (or industry's) coding style guide. \$\endgroup\$ – user_1818839 Jun 9 at 11:48
  • \$\begingroup\$ So it should be ok to have same named files in different libraries? \$\endgroup\$ – quantum231 Jun 9 at 11:58
  • \$\begingroup\$ Did you miss out the tag 'vhdl'? \$\endgroup\$ – Mitu Raj Jun 9 at 12:41
  • \$\begingroup\$ There were versions of Xilinx tools a few years ago that totally messed up handling libraries, but hopefully that has been resolved. So it should be possible; whether it's OK or not depends on how easily confused you and your colleagues get. \$\endgroup\$ – user_1818839 Jun 9 at 13:02
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Is it a good practice to have multiple entities in same file?

Generally not, unless they're very closely related and will never need to be used separately. Very rare IME.

What if entity and architecture are to be kept in different files? What should the files be named in that case?

I have done some projects like that. It becomes useful if some of the code is being generated by a higher-level tool. I simply called the entity file module.vhd and the architecture file module_a.vhd.

Can there be multiple files or entities that have same name where the ports of the entity can be different? Is this acceptable for simulation and synthesis purpose?

An entity is pretty much defined by its interface, so giving entities with two different interfaces the same name can only be confusing.

It's more common to have a common entity, but two or more architectures for simulation/synthesis.

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