There are so much hype and concern over metastability in cross clock domain. If the goal as an ASIC/FPGA designer is to ensure that the signal in source clock get propagated to destination clock even with metastability, consider the case below.
Suppose the input pulse or window signal into the synchronizer is stretched long enough to get latched by the destination clock of the synchronizer FFs twice or more, this ensures that setup & hold are met when the same signal which has been asserted get latched by the same FF 2nd time around; thus the circuit may experience metastability on leading edge of the input signal but the signal will make it out of FF of destination clk. The question is if I can ensure that this happens, do I even need synchronizer FFs (double FFs)? Wouldn't a single FF be sufficient? I guess it depends on what one needs to do with the signal after FF. If I create pulse based on trailing edge signal out of a destination clocked FF, that would work and I would not need to be concerned over whether the circuit experienced metastable condition or not.