Why do CMOS NOT gate designs differ from BJT NOT gate designs?

Question

If you look for an inverter circuit on Google Images, you'll find something that looks like this:

This inverter design has a single NPN transistor. However, on Wikipedia's article about transistor count, inverters are listed as having two transistors. Wikipedia states that this number is based off of CMOS technology, and if you search for a CMOS inverter, you get this image instead. This design does have two transistors: one PNP and one NPN MOSFET. However, I've always been perplexed as to why people do not use the former method for chip manufacturing. After all, Wikipedia would not have stated that inverters required two transistors if the first method was widely used in making chips. Why is there a difference between the CMOS and the BJT method of creating a circuit as simple as a NOT gate?

Answer 1

However, I've always been perplexed as to why people do not use the former method for chip manufacturing.

1. In chip design, resistors take up more area than transistors, and area is one of the main drivers of chip cost.

2. In the BJT design, when the output is low, there is a current running continuously through the resistor. This consumes power and produces heat. In the CMOS design, when the output is low the PMOS device is in cut-off operation and practically no current flows through it, therefore the power consumption is very low.

Answer 2

It's possible to build this circuit with 2 BJT's or one MOSFET

You're reading too much into it.

The difference isn't the technology of the transistor, it's method of circuit operation

In the first circuit, you can STRONGLY SINK current (drive a very strong logic "0"), but you can't strongly SOURCE current (your logic "1" has to pass current through the pull-up resistor, so there will be voltage loss)

The second topology allows you to both source AND sink current very strongly.

The 'weak' or 'strong' output determines the possible fan-out (how many gates can be controlled with this signal) and the speed of the logic transition.

Great question - Gave you a "+1" :)

Answer 3

Your circuit with the bjt is RTL (resistor transistor logic). There’s DTL, TTL, ECL, PMOS, NMOS and CMOS. There’s others as well, but you can research these if you’re interested.

Basically there’s a number of different ways to implement digital logic. Each has their advantages and disadvantages. CMOS tends to be the favourite these days due to its low power.

Answer 4

Several reasons:

Firstly, it's counter-intuitive to someone used to designing with discrete components, but in IC design transistors are cheap and everything else is expensive. In the days when pull-ups were used in IC design they were frequently done with weak transistors instead of resistors.

Secondly CMOS has the huge advantage of very low power consumption when not switching, because the gate of a CMOS transistor is essentially a capacitor and passes no DC current and only one of the transistors is switched on at a time so there is no significant DC current by that path either.

Thirdly because CMOS actively drives the output in both directions, the performance is closer to symmetrical. A device that relies on a pull-up resistor (or weak transistor) will have a fast fall time, but a much slower rise time. Similarly it will have a much lower impedance output when in the low state than when in the high state.

CMOS does come at the price of needing two different types of transistor, that does complicate the fabrication process but it's a small price to pay for the advantages mentioned above.

Answer 5

The short answer is that you are not comparing apples to apples.

Your google image of a single-transistor inverter is not a NOT gate. A bipolar logic (TTL, ECL, LSTTL, Shottkey, whatever) inverter (NOT gate) is much more complex than something left over from the RTL days.

To be fair, you could translate the approach used in a CMOS inverter to bipolar components, with a PNP transistor on the top and an NPN transistor on the bottom. But you cannot just tie the two bases together as you can in CMOS. There would have to be a string of biasing components, such as two resistors and two zener diodes.

Another issue is that TTL output stages are not symmetrical as CMOS ones are, so the inverter input biasing string would have to take this asymmetry into account.

Answer 6

Great Question. As others have stated, the first topology consumes constant power when the output of the inverter is low (logic "0"). Allow me to expand upon this with the MOSFET equivalent. As shown below, the resistor-transistor logic (RTL) inverter has a very similar topology, except for the absence of a resistor on the base (gate in this case, as it is an n-channel MOSFET). Another difference is that there is a capacitance at the output node to GND in this schematic, but that does not affect the answering of the question.

^{simulate this circuit – Schematic created using CircuitLab}

Given the circuit, the same logic applies. If the desired output at Vout is a logic "0", it can be assumed that the input "Vin" is high at a logic "1". This means that the NMOSFET is "on" and current is flowing through it. In this case, the output voltage will fall to 0V (given the capacitance C was previously charged due to a previous "1" output state). Even after the node falls to 0V, there is still a connection between Vcc and GND through the resistor R and MOSFET. Current through the resistor (and the equivalent resistance of the MOSFET) means power dissipation, and this is constant. Thus, this MOSFET version of the RTL inverter also has the same issue.

In the second circuit (the CMOS inverter), "steady state" at the output (either logic "1" or logic "0") means either the PMOS is on and the NMOS off, or the NMOS on and the PMOS off (respectively). In both cases, there is no direct connection between Vcc and GND, so no current at steady state.

EDIT: An Addition if you are Curious - CMOS Power Dissipation

I have noticed other comments mention that the CMOS inverter has been widely chosen out of power considerations for reasons elaborated upon above. This is true. HOWEVER, this does not mean that the CMOS inverter does not have "power problems" of its own. I mention this as these problems have ramifications on current CMOS technology in many of the products we use today. There are actually a few different ways in which power is dissipated in the CMOS inverter, both dynamic AND static. Included below:

Static

1. Subthreshold leakage (dominant source of static power dissipation, at least in CMOS inverters)
2. Junction leakage - This is attributable to the fact that there are two pn junctions in a MOSFET. Under reverse bias, a very small amount of reverse leakage current flows. Typically on the order of a few pico-amps, but can add up when there are many devices in a circuit (on the order of billions, as in modern microprocessors).

Dynamic

1. Capacitive Switching (dominant source of dynamic power dissipation)
2. Transient short-circuit ("crowbar current") - This occurs when both the load and driver are on while a non-ideal (real) input transitions.

I encourage you do look into these if you're curious, as they each deserve their own thread. Just wanted to include to give some more context on power dissipation in these types of circuits, as it has a big impact on the design of digital electronics.