Great Question. As others have stated, the first topology consumes constant power when the output of the inverter is low (logic "0"). Allow me to expand upon this with the MOSFET equivalent. As shown below, the resistor-transistor logic (RTL) inverter has a very similar topology, except for the absence of a resistor on the base (gate in this case, as it is an n-channel MOSFET). Another difference is that there is a capacitance at the output node to GND in this schematic, but that does not affect the answering of the question.
simulate this circuit – Schematic created using CircuitLab
Given the circuit, the same logic applies. If the desired output at Vout is a logic "0", it can be assumed that the input "Vin" is high at a logic "1". This means that the NMOSFET is "on" and current is flowing through it. In this case, the output voltage will fall to 0V (given the capacitance C was previously charged due to a previous "1" output state). Even after the node falls to 0V, there is still a connection between Vcc and GND through the resistor R and MOSFET. Current through the resistor (and the equivalent resistance of the MOSFET) means power dissipation, and this is constant. Thus, this MOSFET version of the RTL inverter also has the same issue.
In the second circuit (the CMOS inverter), "steady state" at the output (either logic "1" or logic "0") means either the PMOS is on and the NMOS off, or the NMOS on and the PMOS off (respectively). In both cases, there is no direct connection between Vcc and GND, so no current at steady state.
EDIT: An Addition if you are Curious - CMOS Power Dissipation
I have noticed other comments mention that the CMOS inverter has been widely chosen out of power considerations for reasons elaborated upon above. This is true. HOWEVER, this does not mean that the CMOS inverter does not have "power problems" of its own. I mention this as these problems have ramifications on current CMOS technology in many of the products we use today. There are actually a few different ways in which power is dissipated in the CMOS inverter, both dynamic AND static. Included below:
- Subthreshold leakage (dominant source of static power dissipation, at least in CMOS inverters)
- Junction leakage - This is attributable to the fact that there are two pn junctions in a MOSFET. Under reverse bias, a very small amount of reverse leakage current flows. Typically on the order of a few pico-amps, but can add up when there are many devices in a circuit (on the order of billions, as in modern microprocessors).
- Capacitive Switching (dominant source of dynamic power dissipation)
- Transient short-circuit ("crowbar current") - This occurs when both the load and driver are on while a non-ideal (real) input transitions.
I encourage you do look into these if you're curious, as they each deserve their own thread. Just wanted to include to give some more context on power dissipation in these types of circuits, as it has a big impact on the design of digital electronics.