I am using Spartan 3E FPGA where the clock rate is 50MHz. I tried to make 1-sec blinking LED program but LED is in a constantly turned off state.

module syScore(
    input clk,
    output complete

reg [31:0] counter1;
reg statusBit;

always @ (posedge clk) begin
    if (counter1 > 50000000) begin
        statusBit = 1'b1 ? 1'b0 : 1'b1;
        counter1 <= 32'b0;
    else begin
        counter1 <= counter1 + 1'b1;

assign complete = statusBit; // E9 LED

  • \$\begingroup\$ you've got an answer to your last question that described why you should never do @(*) for synthesis. Not quite sure why we write answers if you don't read them – or if you don't understand them, don't ask in the comments under the answer. \$\endgroup\$ – Marcus Müller 2 days ago
  • \$\begingroup\$ And your synthesizer should be hitting you pretty harshly for these assignments, so you're ignoring the messages you're getting. This won't work out. We need you to learn to read the things your synthesis tool tells you, we can't be the ones to run your code through exactly the same tools and copy and paste the warnings and errors into an answer. \$\endgroup\$ – Marcus Müller 2 days ago
  • \$\begingroup\$ No, I understood the @ (*). @ (posedge clk) is also constantly turned on. But clk I think running in 50 MHz right? \$\endgroup\$ – Dipnarayan Das 2 days ago
  • 3
    \$\begingroup\$ Then, please read an introduction to verilog, and learn to read the errors your IDE is giving you. \$\endgroup\$ – Marcus Müller 2 days ago
  • 5
    \$\begingroup\$ Also, looking for a question that asks about the difference between = and <=, the first result is this question of yours: electronics.stackexchange.com/questions/569840/… . So, you really haven't been able to follow these answers. I'm sorry,but we can't guide you through verilog design. A structured introduction to Verilog is inevitable here! It will be much quicker to first learn verilog and then ask questions about the things you don't understand than trying to learn verilog by asking question about code you don't understand! \$\endgroup\$ – Marcus Müller 2 days ago

If you just want to write your blinky in Verilog, here's a one-liner:

module test ( input clk, output reg led ) ;

    reg [24:0] n ;
    always @(posedge clk) {n,led} = n ? {--n,led} : {25'd24_999_999,~led} ;

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