An excerpt form the JTAG website

Many silicon architectures such as PowerPC, MIPS, ARM, x86 built an entire software debug, instruction tracing, and data tracing infrastructure around the basic JTAG protocol. Frequently individual silicon vendors however only implement parts of these extensions. Some examples are ARM CoreSight and Nexus as well as Intel’s BTS (Branch Trace Storage), LBR (Last Branch Record), and IPT (Intel Processor Trace) implementations. There are many other such silicon vendor-specific extensions that may not be documented except under NDA. The adoption of the JTAG standard helped move JTAG-centric debugging environments away from early processor-specific designs. Processors can normally be halted, single stepped, or let run freely. One can set code breakpoints, both for code in RAM (often using a special machine instruction) and in ROM/flash. Data breakpoints are often available, as is bulk data download to RAM. Most designs have “halt mode debugging”, but some allow debuggers to access registers and data buses without needing to halt the core being debugged.

Does x86 support this? If not, which architecture does? And more interestingly, at what cost - reliability of state access, inability to capture every sequential state change, perhaps?

  • \$\begingroup\$ I'm pretty sure crossposts aren't generally allowed here. If it belongs here and not there, ask someone to move it. \$\endgroup\$
    – Hearth
    Commented Jun 11, 2021 at 0:59
  • \$\begingroup\$ edit: deleted the post on the other site according to guidance on Meta SE. \$\endgroup\$
    – J.Todd
    Commented Jun 11, 2021 at 1:29
  • 1
    \$\begingroup\$ As the text says, this is not a feature of the architecture x86, but of some designs. So, one x86 CPU might, another might not \$\endgroup\$
    – mmmm
    Commented Jun 11, 2021 at 7:43


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