2
\$\begingroup\$

enter image description here

It is given that Q0[MSB] and Q1[LSB] are both 0 initially and the circuit is edge triggered. The answer says this circuit will generate 2, but I am arriving at 3 and I can't see where I am going wrong.

My thought process is, initially Q0 and Q1 are 0, so the NAND gate will output one, therefore input to D will be 1. When the clock pulse is applied, 1 will pass through the D-Flip Flop and we will have Q0 = 1, now since Q0 is the input to the CLK of the T-Flip Flop and it has gone from 0 to 1, the T-Flip Flop will be activated, Q0 = 1 is also input to T, so it will toggle Q1 = 0 to Q1 = 1, and we will finally have Q0 = 1 and Q1 = 1, which is 3.

My instructor's explanation for arriving at 2:

"we always consider the initial states as the input to the flip-flops. The Q0n and Q1n are the next state values that we get as the output from the flip flop. Please don't get confused with this.

The input to the T-FF is Q0 and not Q0n. For Q1 = Q0 = 0 Input to the D-FF is (Q0 . Q1)' = (0. 0)' = 1 This makes the Q0n = 1 But this Q0n is not the input to the T-FF. Input to the T flip flop is Q0, and it will be active only when Q0 -> Q0n = 0 -> 1. Since for the case Q0 = Q1 = 0, Q0->Q0n is 0 -> 1, therefore, T-FF will be active. Input to the T-FF is Q0 = 0, therefore, it will latch the Q1. Hence, Q1n = 0."

\$\endgroup\$
8
  • 2
    \$\begingroup\$ You may have to account for setup time and hold time. \$\endgroup\$
    – AJN
    Jun 12, 2021 at 7:52
  • \$\begingroup\$ @AJN is the question ambiguous, since nothing is mentioned? Or is there a common sensical assumption for setup and hold time? \$\endgroup\$
    – Yueor
    Jun 12, 2021 at 10:10
  • 1
    \$\begingroup\$ To the second flip flop, the 1 appears at the same to T and clock. AFAIK, the input should appear slightly earlier than the clock edge. See Timing section in this article. I am not sure though. Are these concepts taught by your instructor? \$\endgroup\$
    – AJN
    Jun 12, 2021 at 11:31
  • \$\begingroup\$ My instructor did tell me the definition of setup and hold time, didn't go into its significance in the actual example circuits though. I'm confused as hell about what's happening here to be honest, also, since you said the input must be present slightly earlier than the clock edge, does that mean I should take T = 0 when the T-Flip Flop is activated, because we have 0 as input right before the clock pulse. \$\endgroup\$
    – Yueor
    Jun 12, 2021 at 12:07
  • 2
    \$\begingroup\$ Yes. T=0. But, I would either 1) wait for someone to answer this question where it is accounted for, or 2) try to do a simulation that takes this into account or 3) look up a text book where a problem which takes this into account is worked out clearly. Especially since a answer containing a simulation result is posted which says otherwise. \$\endgroup\$
    – AJN
    Jun 12, 2021 at 12:10

2 Answers 2

2
\$\begingroup\$

Your instructor is saying that the next state will be Q0 = 1, Q1 = 0 (which is not “2” by the way).

Based on your instructor’s explanation, I think what’s happened here is the diagram is drawn wrong: the clk was intended to be connected to the clock input of both flip flops. The explanation would then be correct: the T flip flop’s clk edge would occur while Q0n was still 0 so its output would remain 0.

The way it’s drawn (T and clk tied together) there is a likely metastable condition where the output is indeterminate because of setup/hold violations, which I’m sure was not an intended aspect of this question.

\$\endgroup\$
4
  • 1
    \$\begingroup\$ Agreed. It’s almost certainly drawn wrong. \$\endgroup\$ Jun 12, 2021 at 21:10
  • \$\begingroup\$ Just to make sure I am understanding this correctly, the problem with this circuit is that the input to the flip flop is changing simultaneously along with clock, and if we have a common clock, as you suggested, that problem is eliminated, here, the inputs change after the clock pulse. \$\endgroup\$
    – Yueor
    Jun 13, 2021 at 6:01
  • 1
    \$\begingroup\$ Yes, you understand correctly. With a common clock it is a standard synchronous design: both flops see the clock edge at the same instant, and the state of D (or T) at that point determines the next state. It takes some finite time to propagate D (or T) to Q. By the time Q0 changes the clock edge has come and gone on the T flop. Having the D (or T) change at exactly the same time as the clock is a worst case scenario: the output is unpredictable. \$\endgroup\$
    – td127
    Jun 13, 2021 at 6:37
  • \$\begingroup\$ Thank you for more details and your answer, I really appreciate your help. \$\endgroup\$
    – Yueor
    Jun 15, 2021 at 9:27
2
\$\begingroup\$

The answer should be three as you clearly explained. I have done the simulation in Logisim which also gives three after one clock pulse.enter image description here

\$\endgroup\$
13
  • 1
    \$\begingroup\$ In your figure, T will be 1 at the first clock pulse. \$\endgroup\$ Jun 12, 2021 at 7:07
  • 1
    \$\begingroup\$ I think that the answer should be three in every way. \$\endgroup\$ Jun 12, 2021 at 7:39
  • 1
    \$\begingroup\$ Which book are you using? He is obviously wrong. \$\endgroup\$ Jun 12, 2021 at 7:44
  • 1
    \$\begingroup\$ There is a book called "Digital Design with an introduction to Verilog HDL" by Morris Mano and Ciletti which is very good for beginners. There are various practice problems too . \$\endgroup\$ Jun 12, 2021 at 7:55
  • 1
    \$\begingroup\$ What are setup time and hold time for each flip flop you are you using in the simulator? \$\endgroup\$
    – tim
    Jun 12, 2021 at 8:45

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.