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Reading some scientific journals I saw that research groups often use a silicon wafer with appropriate dielectric constant/relative permittivity and then build a microstrip (coplanar SGS or edge coupled SG) on it via lithography. While I saw that you can simply order doped silicon wafer with high resitivity (>5000 Ohm cm), I'm wondering what the point of such a thin (300-1000 nm) SiO2 surface layer is?

And if you calculate the impedance of such a waveguide on this substrate, do you still use the dielectric constant of the thick (around 400 um) silicon (around 11.9) substrate, or that of the thin SiO2? The groups operate this waveguide at low voltage, feeding in voltage with picoprobes on the lithographically structured waveguides.

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Presumably your waveguide will have to be conductive in order to transport the signal. So using high resistivity Si isn't going to help you. What you need is lateral resistivity that is low (highly conductive) whilst vertical conduction is low (high resistivity).

In semiconductor technology you have two isolation mechanisms, 1) dielectric (i.e. insulator) isolation and the 2) Junction isolation. I think dielectric isolation is obvious in context, you have a thin layer of SiO2 to keep the Metal layer and the substrate separate. Junction isolation means that you would form a junction through implanting dopants and converting the substrate into a opposite polarity. What you would be building is an extended diode with most likely a N-type conductive region on a P-type substrate. Diodes have capacitance which is also voltage variable. Do in doing this you would get higher capacitance which because of it's non-linearity could cause distortion (depending upon how you operate it).

Modelling this means as a good first order approximation of using the dielectric of the Si substrate as you suggest, depending upon your parameters you may have to bring in the di-electric (SiO2) but the permittivity of the SI is so high that the E-Field laines will be sucked into that.

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