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I have an ISO driver with the following params: Peak source current = 4 A, Peak sink current = 6 A, Sink resistance = 0.55 ohm, source resistance = 5 ohm.

How do I calculate the time between the rise/fall to 50% Voa to Vth of the FET? The FET has 1 ohm gate resistance, and an external 47 ohm get resistor, as well as an external Vgs capacitor of 10 nF, image below:

enter image description here

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  • \$\begingroup\$ Why the external Cgs capacitor is needed? For the correct calculation you should look into a datasheet for Gate charge VS. Vgs, then read some paper from TI, Infineon, IOR, Analog Devices, LT...which describes this with all needed equations. \$\endgroup\$
    – Marko Buršič
    Jun 14, 2021 at 8:12
  • \$\begingroup\$ to slow opening and closing of fet \$\endgroup\$
    – Jonathan
    Jun 14, 2021 at 8:18
  • \$\begingroup\$ Which FET, and what is the load on the Drain? \$\endgroup\$
    – Bruce Abbott
    Jun 14, 2021 at 10:29

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