I'm looking to implement a phase lock in an FPGA without using any external components (other than the ADC). For simplicity locking to a simple binary pulse is adequate. The frequency of the signals is ~0.1-1% of the clock. I can't use the onboard clock PLL's because they are typically:
- Not configurable (set during synthesis).
- Don't support the frequency I need.
I've been sorting through the literature and found a few binary phase locked loops. Most notable a "pulse steal" design that I can post a link to if desired. I have implemented and synthesized with some success, but its jitter and lock range was not as good as advertised. I've also had success using a external DVCO, but I would prefer if I can implement everything on chip.
A digital circuit design or even a hint in the right direction would be helpful (I've been banging my head against this for a while), a proven FPGA implementation would be wonderful but not expected.
The actual DPLL design that I used has a "Random Walk Filter" as the loop filter (not the "pulse steal" described earlier, going through my notes that didn't work to well), which then drives the clock pulses to the DCO. The lock-in range is set via divider in the DCO. The sensitivity of the loop is established by varying the length of the random walk.
The paper in which this is found is cited at the end of this post. After implementing parts of it myself, I found that it was actually already implemented on OpenCores, however it turns out that in the last few months the project was deleted but I have the Verilog files saved if anyone wants them.
Yamamoto, H.; Mori, S.; , "Performance of Binary Quantized All Digital Phase-Locked Loop with a New Class of Sequential Filter," Communications, IEEE Transactions on , vol.26, no.1, pp. 35- 45, Jan 1978