Is there a general rule for p-FET's that explains when Vg can can be higher (or more negative) than Vs? I had posted a while back and a helpful person explained I needed to keep Vgs higher than Vds, otherwise the FET could overheat or malfunction. I think we were discussing n-FETs at the time, so for a p-FET I believe that means Vgs should be more negative than Vds. Is that correct?

For instance, I have an FQP12P10 rated for Vgss +/- 30V.

I'm suppling Vg from a 48V nominal source (Vhouse) and using a 68K/47K voltage divider that outputs 16.3 V to 24.5 V depending on battery state of charge (can be 40V to 60V at extremes).

Vs is supplied by a separate 12V nominal source (Vstarter) that can vary between 11V and 15V. Both Vhouse and Vstarter share a common ground.

When Vhouse is at 48V nominal, the circuit outputs 0V. When Vhouse is at 0V, it outputs 12V nominal. That is what I need.

But apparently Vhouse actually goes to 6V during BMS cutoff, not 0V, and it will supply enough current at 6V to power an LED, so presumably it could easily power a p-FET gate.

When I test my circuit with Vhouse at 6V, it appears to work the way I want, with the gate switched off, and 12V on the drain. But I'm not sure why. I measure Vg at 2.4V, and Vs is at its usual 12V. But is this condition okay, or is it damaging the p-FET like the person suggested it might? (if I understood them correctly, which I may not have).

I'm hoping the circuit is okay as described. I've left it in this state for hours and there's no warming of any devices or unusual behavior. The circuit will only drive an LED and another logic device that will use a few mA at best, so the p-FET will never conduct any serious current.

But I'm a bit confused as to the relationship between Vg, Vs, and Vd, and when one must be higher (or more negative) than the other. Any help is greatly appreciated.

Here is the basic schematic: enter image description here

And here's a photo of the actual prototype when Vhouse is at 6V. The p-FET gate clearly isn't switched off. That's actually good for my application, but I don't understand why. You can see the the LED is light and I get a clear 12V measured on the drain (white wire running down to bottom where LED sits). When connected to 48V, it works as expected. The LED is out, Vd is 0V. When I use the pushbutton tester to shunt R1 to ground, the LED lights up and 12V is output.

enter image description here

  • 1
    \$\begingroup\$ How does Vout and Vstarter12V relate to GND? \$\endgroup\$
    – winny
    Commented Jun 14, 2021 at 19:52
  • \$\begingroup\$ Forgot to say Vstarter and Vhouse share a common ground. Good catch. Vout is relative to that common ground. \$\endgroup\$
    – VanGogh66
    Commented Jun 14, 2021 at 20:19
  • \$\begingroup\$ "When I test my circuit with Vhouse at 6V, it appears to work properly. Vgs is at -2.4V, Vds is at -12 V" - According to my calculations Vgs should be -9.55V (since Vs = 12V and Vg = 2.45V). How do you get -2.4V? \$\endgroup\$ Commented Jun 14, 2021 at 21:15
  • \$\begingroup\$ @bruceabbott I may have misstated. The gate voltage (output of the voltage divider) is -2.4V relative to ground when Vhouse is 6V. Is that Vgd? I'm honestly a bit perplexed as to the exact relationship between gate, source, and drain. I understand the big picture, but not how they are influenced by each other. \$\endgroup\$
    – VanGogh66
    Commented Jun 14, 2021 at 21:53
  • 1
    \$\begingroup\$ Please edit you question to correct the voltages. Your battery and 12V supply are positive voltages, right? Then the Gate voltage relative to Ground is +2.4V and voltage on the Drain should be close to +12V (since the FET is well turned on). Vds (voltage from Drain to Source) should be close to 0V. \$\endgroup\$ Commented Jun 14, 2021 at 22:05

1 Answer 1


Your PMOSFET probably has a body diode between the drain and source. It's not so important that |Vgs| > |Vgd|, but that Vs > Vd. Otherwise, if Vs-Vd gets too negative, the body diode will happily conduct until fried.

  • \$\begingroup\$ In my circuit above Vs just passes right through to the drain. And the drain never sees any voltage input, only a small load (LED) and another logic circuit. Do you think I'm okay as described? Why do you think -2.4V at the gate and -12V at the source leaves the FET conducting? Just not above the gate threshold? I thought @nanofarad had explained that p-mosfet gates and sources were related somehow, and that I needed to account for this. \$\endgroup\$
    – VanGogh66
    Commented Jun 14, 2021 at 21:06
  • \$\begingroup\$ Assuming you didn't intend those negative signs in front of the voltages, you should be fine. If Vg < Vs - Vgth, the FET will be conducting normally. Depending on how much current you're drawing, Vd should be about equal to Vs. \$\endgroup\$ Commented Jun 15, 2021 at 14:05

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.