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I am using a FIFO as a temporary memory block to store values and then perform some calculations between the neighboring values once the FIFO becomes full. After the calculations are finished, I would like to flush the FIFO and have the system ready for the next set of data entries.

My question is, do I need to flush the FIFO or can I write over the values that were once in the FIFO? I do need to eventually synthesize this design on an FPGA so I am not sure which option is the viable.

Thanks for the help!

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    \$\begingroup\$ That question cannot be properly answered without knowing what part you used and how it is connected. It would help if you posted the schematic and links to the appropriate hardware devices. \$\endgroup\$
    – Gil
    Commented Jun 15, 2021 at 1:38
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    \$\begingroup\$ The data themselves are just random 1 or 0s. As long as you don't have any safety (or others) concern, you can simply FLUSH the memory by resetting all control logic. \$\endgroup\$
    – Light
    Commented Jun 15, 2021 at 2:07
  • \$\begingroup\$ @Light What will happen to the existing data entries if I do not flush it with the control logic? \$\endgroup\$ Commented Jun 15, 2021 at 2:42
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    \$\begingroup\$ Depends on the FIFO implementation. And you haven't specified it \$\endgroup\$
    – Mitu Raj
    Commented Jun 15, 2021 at 4:33
  • \$\begingroup\$ If this is a built-in FIFO, then commonly, reading from a FIFO removes the data from it. \$\endgroup\$ Commented Jul 6, 2021 at 9:08

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Most common approach would be implementing a circular buffer. You do need a write and read pointer (index), the difference WR-RD is the FIFO size. FIFO half full would mean (WR-RD)>= size/2, then you can calculate elements between RD and WR pointer, in the meantime the FIFO could receive new data.

You do flush nothing, padding zeroes into a buffer takes the same amount of time as writing new data, moreover zeroes also represent data. The easy way to flush is RD=WR, so the FIFO has now 0 stored values (WR-RD=0).

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