And is there a chance of re-emergence of VHDL in commercial VLSI/EDA professions as an in demand skill?

  • 2
    \$\begingroup\$ It has? Damn, this mountain of work before me must be imaginary. \$\endgroup\$
    – DonFusili
    Commented Jun 15, 2021 at 7:17
  • \$\begingroup\$ @DonFusili If this is not so, then why there are more jobs visible on platforms like LinkedIn with tags like Systemverilog than VHDL? \$\endgroup\$
    – lousycoder
    Commented Jun 15, 2021 at 7:24
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    \$\begingroup\$ I think you are talking about US and all. In European countries, I think VHDL is still more popular. And in defence/avionics sector in my country, VHDL is preferred. \$\endgroup\$
    – Mitu Raj
    Commented Jun 15, 2021 at 7:37
  • 1
    \$\begingroup\$ @lousycoder systemverilog is useful mostly for verification engineers. Linkedin is an elaborate social network and the things you're shown are prefiltered by what it thinks is relevant to you. You're probably looking specifically at entry-level jobs or verification engineer jobs. Generally, you'll find that people will be surprised if you tell them information on social media is unbiased. That's the opposite of true. \$\endgroup\$
    – mmmm
    Commented Jun 15, 2021 at 8:26
  • \$\begingroup\$ @mmmm yes, my observation was only for entry level jobs. I think verification jobs are more visible. \$\endgroup\$
    – lousycoder
    Commented Jun 16, 2021 at 19:06

1 Answer 1


Simply put: it hasn't, not for the implementation at least.

sv has become more popular as the verification framework, and conversely as the top-level integration language, because it's easier to use UVM in sv. Also, VHDL is a horrible verification language.

That doesn't mean that large parts of the actual designs are not still written in VHDL, most digital designs I've worked on in the last few years have been 50-50 verilog and VHDL. Pretty much the same as I've seen in the last few decades. FPGA projects tend to lean more towards VHDL, ASICs more towards verilog, but the differences are small in my experience.

So the increase in demand for SystemVerilog you see is (almost) purely for verification, not design and implementation.

  • \$\begingroup\$ A lot of verification IS still done in VHDL; there are toolkits like OSVVM and UVVM to make the job easier. \$\endgroup\$
    – user16324
    Commented Jun 15, 2021 at 10:03
  • \$\begingroup\$ @user_1818839 Yeah, I know, and they all suck badly enough at their core tasks that they don't even deserve a mention. \$\endgroup\$
    – DonFusili
    Commented Jun 15, 2021 at 10:12
  • \$\begingroup\$ @DonFusili Then I guess you never learned and/or tried OSVVM. In the 2022 Wilson Verification Survey, in FPGA 56% of the market uses VHDL for verification. Also in FPGA 28% of the market uses OSVVM (that is half of the community doing verification in VHDL). \$\endgroup\$
    – Jim Lewis
    Commented May 5, 2023 at 19:01

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