For multiplexers, what are the pros and cons of Three-State Buffers vs "Straight Gates"?

Question

This came up from my previous question when looking more closely at multiplexers. Wikipedia article shows two ways of implementing them. One with some Three-State Buffers, and the other that's just "straight gates", but notice those AND gates have 3 inputs.

So is there any significant engineering different between a tri-state buffer and a 3-input AND gate? Is one more expensive to manufacture than the other? Does one cause bigger design issues? More power requirements?

What are the advantages/disadvantages of them for the purposes of multiplexers?

(My foreseen application is CPUs and other computer architecture.)

Answer 1

For small multiplexers it doesn't matter. Large ones, a gate-implemented mux will take more area and have longer delay. So these use a different structure. More about than in a moment.

3-state buffers don't work well on ICs as this approach can leave the output line floating. This can be overcome with a 'weak keeper' on the line, but there's another way.

Chips with large selectors (like RAMs) don't use 3-state buffers or data path gates to construct multiplexers. Instead, they use transmission gates. These reduce the transistor count for the select element to just two FETs per selected data line. They also have less delay than either a gate or 3-state buffer approach.

Bonus: transmission gates work in both directions. This is used to some advantage in RAMs which share the same path for read and write. They also work on analog signals.

Answer 2

In ASIC design (and probably FPGA design as well), internal logic tri-state gates are to be avoided unless absolutely necessary. There are several reasons why that is the case, but the short version is that the rule keeps you from shooting yourself in the foot, and isn't really costing you area. Note that within a gate boundary, it's fine as long as the output is a standard CMOS output.

^{simulate this circuit – Schematic created using CircuitLab}

The two inverters generating the inverted select signals are not shown for either schematic

Comparing these two topologies, the tri-state topology provides significantly less propagation delay from your data inputs to your output. Not shown is the four NAND + four INV gates needed to generate the select signal for each individual tri-state gate. That's a total of 46 transistors for this topology, and two-ish gate delays from A->Y. There will be greater current consumption when switching between selected lines as there will be some shoot-through current on the tri-state node (e.g. from NOT1 to NOT3).

The fully static gate implementation adds the decoder into the data path. At this point, you could make a 4-input NAND to replace the output stage, but it's a bunch of trade-offs of whether you want 2 faster stages, or one slower 4-input gate stage. As drawn, this comes to 42 transistors, just a bit smaller. The S to Y timing will probably be a bit faster and will not short out two gates.

Neither design will be fun to lay out well as a single gate in an ASIC library.

Answering the questions

• The timing differences depend on use cases - Faster A->Y time would favor the tri-state gate, while faster S->Y time would favor the static gate. The overall difference is not very large.
• The static design is probably a bit smaller at 42 transistors compared to the 46 for the tri-state gate as drawn.
• The tri-state design has shoot-through current between tri-state inverters when the select line changes. Neither designs are glitch free.

Overall, from an ASIC perspective, I would probably pick the tri-state design most of the time. If you're in a FPGA, it doesn't matter either way (it gets handled by the LUT)