I'm currently working on my first commercial design and this is the final prototype before I finalise the design, so I want to get it as correct as possible. My PCB has 12V, 5V and 2 x 3.3V(digital) and a separate 3.3V(analogue) rails. The reason for having 3 different 3V3 is due to power consumption, I'm using two MCUs and some analogue circuitry so a single 3V3 isn't viable if I need a heatsink.

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FYI M3 is a DC-DC module with all the caps etc. on it. The final design will have a dedicated switching circuit.

12V-T isn't set in stone yet. This rail will be used for pulsing large current into a coil (1A+) but I may swap out U1 for 15V, 18V or 24V, I need to test experimentally with this board. Vtemp will be +3V from the regulator output depending on which voltage is decided. In this example it is 15V.

This design has a combination of sensitive analogue circuitry, digital circuitry with various voltage requirements and a large current pulsing circuit. I'm limited to a 4 layer PCB due to costs. I'm not splitting the ground plane as the consensus seems to be that there is no consensus and that you can actually make things worse. I intend to simply group all the separate circuitry (except the pulse) into their own areas and have them on the top layer. The second layer would be an unsplit ground. The third layer would be for the smaller voltage rails (5V, 3.3V etc.) and the bottom layer would be my pulse circuit: enter image description here

Q2A receives a clock pulse and J13 is a header that connects a coil of wire.

Now my questions:

  1. Does it make sense to separate the circuitry that has the large pulsing current and to place it on to the bottom plane, if the other circuits are on the top? This circuit generates large back EMF (250V+) across Q4 that is necessary for the design.
  2. Can I just have the 12V-T rail as large traces on the bottom plane alongside the circuit, rather than have it's own plane? Would this be better than having it as part of the dedicated power plane?
  3. If I dedicate the third plane for the other power sources/voltage rails, do I just physically split the copper plane in to sections and then connect to the corresponding components through vias?

Any ideas or advice would be appreciated. I've already got a good idea of what direction I want to go in but I want some confirmation/advice that I'm not doing anything obviously stupid.

  • \$\begingroup\$ What's connected to "CoilTX"? Could you make due to with a simple low side N-FET switch instead? \$\endgroup\$
    – winny
    Commented Jun 16, 2021 at 12:32
  • \$\begingroup\$ Unfortunately no. Due to historical reasons and the way the coil is manufactured/connected to the board it has to be high side FET so one side of the coil is grounded at all times. \$\endgroup\$
    – ChrisD91
    Commented Jun 16, 2021 at 12:49
  • \$\begingroup\$ I see. Just checking. \$\endgroup\$
    – winny
    Commented Jun 16, 2021 at 12:52

2 Answers 2


Layer changes don't make a difference. Distance is your friend, keeping lively electric and magnetic fields away from sensitive traces.

Secondly, keep current flow/return paths of different sections, as separate as possible. Avoid digital currents running over/through sensitive analog areas; avoid power switching currents running through digital or analog areas. Consider that return currents follow the path of least resistance at DC, but the path of least impedance at AC -- in particular, the image current underneath and around the trace.

More important to success may be common mode interference. Note that, when the coil is pulsed, its average voltage (lead1 + lead2) / 2, the common-mode voltage, is driven to half the pulse amplitude. Whatever capacitance the coil has to surroundings (capacitance to space, if nothing else, but depending on how close it is to the circuit, or anything else conductive), is displacement current returned to the circuit along ground. This may be even worse if the coil is grounded (as hinted by the low-side ground stipulation).

Ground bounce will be read as a blip on the scope, when probing anywhere, even probing ground to ground (i.e. attach ground clip to probe tip and poke that to circuit GND). We conclude that, the voltage of the whole board is moving with respect to scope GND (and, most likely, by extension, to surroundings generally), and you are measuring the voltage drop across the ground clip itself -- this is a rate-dependent effect, and the clip lead's inductance (~100nH) is significant in the 10s of MHz up. If you're getting switching edges below 100ns, expect such interference.

CM interference isn't necessarily a problem, but it depends what signals you're bringing in, and how. If nothing else is connected to your board, then CM currents flow along the ground plane, distributing CM voltage across the board; as RF currents, they preferentially flow along the edges, so keep small-signal stuff inward from the edges, say by a few hundred mil, or towards the center of the board, and it'll probably be fine. If you have other connectors, currents will flow onto them as well, and this injects noise into cables with poorly-joined shields, or pairs driven with unbalanced impedance.

The ground plane acts as a crude shield around the circuitry. It would be better if it extended up and around the circuit as a shield can, or a metallic enclosure. Topologically, we can think of a ground plane as a shallow box, with one side opened up and removed: it doesn't block as well anymore, but it still does a good enough job, say for most commercial purposes (logic-level signals typically shielded below regulatory emissions limits, immunity pass).

If the coil is, in fact, one-side-grounded, extend and widen that ground path as much as possible, into or around the PCB, so that the PCB plane is a contiguous extension of it.

There isn't much else I can say about the system (or, whether the concentration on CM interference will even be particularly helpful), without complete schematics and drawings; but as you can see from the length of this post already, EMC topics are very broad, and generally make poor questions here I'm afraid. I would encourage alternatives to EE.SE for EMC questions:

  1. Ask at a more conversational forum, such as EEVblog. You might still not get an answer, or a lot of bad ones, but you're more likely to get some kind of engagement.
  2. Hire a professional, who then has the ability to take on the entire scope of your design, while protecting your interests under NDA if need be. This isn't cheap, but EMC is a complex topic of great commercial importance, and it is very worthwhile from a business standpoint.
  3. Read and study the subject, in as much detail as possible. In particular, the EM and RF courses in an EE curriculum (may include masters level topics) to obtain a theoretical foundation; treatises such as Electromagnetic Compatibility Engineering, by Henry W. Ott; and lots of experience doing practical labs, using relevant equipment, how EMC testing is done generally; regulatory standards; etc. It takes years to develop a firm understanding of the subject; pace yourself, and try not to worry about not grasping things at first, or quickly. It's a broad and interconnected subject, and takes a long time to knit together a sturdy, connected web of knowledge.

How do you plan to pre-place your "boards"?

External connectors? On one edge? Two edges?

First assignments? Example : Two layers for supplies distribution (+5V, GND), as you have some connections... One layer for signals, One layer Gnd1 for ground signals (quasi no current, in general weak current).

Some cautions to follow: (not limited) Well and shortest decoupling of power supplies of every OPamps... Well and shortest decoupling of power supplies of every digital circuits... Keep geometric "area" of "high current conducting lines" as little as possible... Only one GND point connection for all "gnd", near GND general power supply, on side (15V)...


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