# Why impedance matching for only certain signals and not for other signals

I have a question.

Usually, in normal communication interfaces such as I2C, SPI or even normal GPIO interfaces, we don't associate them with impedance matching.

But for certain signals (I don't know which signals are those. But I have read high speed signals require impedance matching) , we require impedance matching.

Why is it for some signals you require impedance matching and for other signals we don't associate with impedance match. Even SPI also transfers data at a max rate of 10Mbps.

Where is the line drawn and why is it drawn?

## 5 Answers

The important thing is the rise time (not the pulse repetition rate) of the signal, compared to the length of the trace.

If the signal can make several round trips of the line between the driver and receiver during the rise time of the signal, then we can ignore the transmission line effects. With a trace 200 mm long, which is about 1 ns electrical length assuming typical construction, a rise time of several nanoseconds will be slow enough to work unterminated. A sub-ns risetime will certainly cause problems unless the trace is properly terminated.

The easiest way to see what's going on is to use a simulator. This is the circuit I'm going to simulate. A 5 V step with a 10 nS risetime feeds a 100 Ω transmission line. The series termination resistors will either be 10 Ω for a mismatched driver, or 110 Ω (more or less matched, enough mismatch left to see what's going on). The shunt termination is either absent, or a nearly matched at 110 Ω.

simulate this circuit – Schematic created using CircuitLab

Let's start off with the ideal case, with shunt termination, below. The shun resistor is 110 Ω, the series resistor is 10 Ω, to represent a finite driver output impedance. This is expensive in terms of drive power, as the driver has to drive the full impedance of the line with the step, and the termination resistor at DC.

The line is 40 ns long, which means the input step has made its full swing well before any reflections return.

You can see the effect of the small mismatch as the reflections return, but they only produce a small ripple on the final waveform. The switching waveform is ideal at all points on the transmission line.

Now let's use a cheaper form of termination, series, below. The series resistor is 110 Ω with the shunt open circuit. The driver only has to drive 210 Ω with the step, and no DC driver power.

We only have a clean waveform at the end of the line. The start and midpoints of the line go up to 2.5 V initially, due to the voltage division between the series resistor and the line impedance. They stay there until the reflection returns from the end of the line and lifts the voltage to the full 5 V. If we had logic gates connected to those points, especially clock inputs, they could oscillate. Series termination can only be used to drive a single receiver at the end of the line.

What happens if we don't terminate a line this long? The series resistor is 10 Ω, a fairly strong driver with no attempt at matching, below.

Without the voltage division of the series resistor, the line goes up to more or less the full voltage at once. However, when the reflection returns, it now boosts the voltage to double, which will cause substrate diodes to conduct at the inputs to the gates. These are only designed to protect the inputs from EMI, and current through them could disturb normal operation, possibly even latchup.

Even worse, when the next reflection occurs, the voltage dips below 2.5 V, meaning a clock input will see a second edge. As time goes on, the reflections subside, energy gradually being absorbed in the driver output resistance. At some point, the reflections will stop switching any clock inputs on the line.

Finally, let's have a look at a short line, below. It's still unterminated, with no shunt resistor and a 10 Ω series resistor. The input step risetime is still 10 ns, but the line has been shortened to 2 ns, roughly 16" or 400 mm of track on a board.

When the reflection gets back to the source end of the line, the source voltage has not risen very far, and the reflected signal is still quite small. Although you can see the reflections do influence the trajectory of the waveform, the signal is still 'clean enough'. There are no extra transitions crossing 2.5 V. The ringing at the top of the waveform will probably not be turning on any substrate diodes in the receiver.

At some point between 2 ns and 40 ns, the waveform will breach some threshold of acceptability. Perhaps >1 V overshoot? Perhaps the leading edge of the voltage waveform becoming non-monotonic? Perhaps the waveform dipping below the switching threshold? Any particular situation might have its own criterion for successful operation. But well away from the threshold, we can easily see what we mean by 'short enough to be OK', and 'long enough to give a problem'.

• I find it difficult to understand the concept when you considered the length of the trace as 1ns. Could you please rephrase your answer in simple terms with little more details? – Newbie Jun 17 at 10:25
• The speed of light is about 300mm/sec, an electrical signal in copper moves at about half that rate. If the signal reaches the end of the track well before the transmitter changes state then you don’t need to worry about transmission line effects. If the signal changes state in a time less than the propagation delay then you do need to take transmission line effects into account. – Frog Jun 17 at 10:53
• 300 mm/second seems mighty slow @Frog – Andy aka Jun 17 at 12:22
• @Newbie here AN-610 is a note from Fairchild about their FACT CMOS logic. The lengths/times are tailored to their particular risetimes. They mention their input diodes can clip the overshoots which can be enough to get proper performance in some circumstances. – Neil_UK Jul 10 at 5:10
• @Newbie Yes, it works for me as is, firefox 89.0.2, linux mint 20.1, UK. Try it with an http:// in front like this notes-application.abcelectronique.com/009/9-12500.pdf. <edit> I put http in the link here, but the render and the hover shows it without. Never really quite understood how this site or browsers treat links, a lot of stuff seems to get defaulted. – Neil_UK Jul 10 at 10:32

Impedance mismatch causes signal reflections, so for each edge in the signal, additional edges are generated as the echoes and echoes of echoes overlap it.

This can be tolerated as long as the amplitude of the reflection is small, or the time delay of the reflection is short enough that this only leads to a bad shape of the transition edge, but doesn't affect the symbol itself.

The time delay of the reflections is defined by the length of the transmission line between points with mismatches, and the speed of transmission defines the symbol time.

So, impedance matching is required for high speeds or long transmission lines, and with higher speeds, the threshold for "long" shrinks.

• Thank you very much for the answer. So, effectively, the term "Impedance mismatch" is applicable to all the signals, right? Irrespective of whether its is normal GPIO, or I2C Clock or SPI clock or any other interface. From your answer , what I understand is that, the term is more important on high speed and long length signals. – Newbie Jun 17 at 8:47
• @Newbie, yes. Basically, we ignore it for slow digital signals that we are sure can be recovered on the other side, because for a digital signal, the information will still be transferred. – Simon Richter Jun 17 at 8:51

Impedance matching is always a concern. You always have to pay attention to it. However, with something like an I2C bus, there is a defined way to drive the bus (in this case open collector output with a bus pullup resistor of say 470R) which already takes account of this.

Impedance matching is a universal electrical concept which applies any time you try to pass a signal from one circuit to another.

• Thank you for the answer. But why don't we often use the term "Impedance mismatch" with certain signals like normal GPIO or I2C or SPI but rather use with certain high speed signals? – Newbie Jun 17 at 8:45
• The way things are done is different when we are dealing with a "transmission line" (i.e. at high frequency). At low frequency, we want to drive a high impedance from a low one, to transfer as much signal as possible, and we pretty much ignore the little bit of copper that connects the two circuits. When we are dealing with a transmission line, we aim to match the characteristic impedance of the line, to prevent reflections which cause distortion. These are both examples of "impedance matching", it's just that what is being matched to is different, and the reasons behind it. – danmcb Jun 17 at 8:54

The line is VERY loosely drawn at about when the signal trace length approximates a quarter of a wavelength of the signal it is carrying. However, much depends on shielding, characteristic impedance, how its driven and so forth. It also depends on the maximum frequency component of the rise and fall times of the signal. So if (say) you have a 100MHz digital signal that is 5ns high and 5ns low. If you want reasonable edges that is a 1ns rise and fall, or 1GHz. In terms of wavelength, that's roughly 30cm. A quarter of that is 7cm, so you almost certainly need impedance matching to minimize reflections etc.

• Thank you for the answer. Could you tell me the reason why the line is drawn at "signal trace length approximates a quarter of a wavelength of the signal it is carrying" ? – Newbie Jun 17 at 8:49
• @Newbie It's all a bit vague unless you do the maths, but this will give you an idea en.wikipedia.org/wiki/Monopole_antenna – Dirk Bruere Jun 17 at 11:48

You may wonder why traces of some interfaces are not analyzed by the transmission line theory. Following is simple analysis of impact of trace length: Referring to input impedance of lossless transmission line, $$Z_{in}(l) = Z_0 \frac{Z_L + j Z_0 tan(2 \pi l / \lambda)} {Z_0 + j Z_L tan(2 \pi l / \lambda)},$$ if $$\l \ll \lambda\$$, $$Z_{in}(l) \approx Z_L,$$ anywhere along the trace and the effect of transmission line can be neglected. There is no need to concern with reflection caused by impedance mismatch because the circuit can be treated as a lumped component one.

Note that ringing of pulses can still happen depending on poles of $$\Z_L\$$.