# Is the answer to this JFET amplifier excercise right?

The problem is the following:

*TYU 4.14 For the circuit shown in Figure 4.59, the transistor parameters are: IDSS = 6 mA, |VP| = 2 V, and λ = 0. (a) Calculate the quiescent drain current and drain-to-source voltage of each transistor. (b) Determine the overall small-signal voltage gain Av = vo/vi . (Ans. (a) IDQ1 = 1 mA, VSDQ1 = 12 V, IDQ2 = 1.27 mA, VDSQ2 = 14.9 V; (b) Av = −2.05)

I am getting all results right except for Av. I am getting Av = -7.72 vs the book answer Av = -2.05.

Is the book correct?

The problem is from Microelectronics 4ed (Neamen), in page 263.

Let us see what we get.

First, we need to find the $$\I_{D1}\$$ and $$\I_{D2}\$$.

How could the Gate-Source potential difference be neglected?

If we do some math we are going to get these results:

$$\I_{D1} = 0.996258mA \approx 1mA\$$ and $$\I_{D2} = 1.27mA\$$

Now we can find the JFET's transconductance

$$\g_{m1} = \frac{2I_{DSS}}{|V_P|}*\sqrt{\frac{I_D}{I_{DSS}}} = 2.45mS\$$

$$\g_{m2} = 2.76mS\$$

As you can see so far I've got the same result as you get.

Now the AC small-signal analysis. As you can see $$\Q_1\$$ is a common-source amplifier. And the voltage gain of this stage is:

$$A_{V1} = - g_{m1}*R_{D1} = -9.8V/V$$

The second stage is a common-drain amplifier.

And we can find the (voltage) gain of this stage this way:

simulate this circuit – Schematic created using CircuitLab

$$V_O = I_{S2}*R_{S2}||R_L = (V_{G2}-V_O)*g_{m2}*R_{S2}||R_L$$

$$V_O = g_{m2}(R_{S2}||R_L) V_{G2} - g_{m2}(R_{S2}||R_L) V_O$$

$$V_O + g_{m2}(R_{S2}||R_L) V_O = g_{m2}(R_{S2}||R_L) V_{G2}$$

$$V_O(1 +g_{m2}(R_{S2}||R_L)) = g_{m2}(R_{S2}||R_L) V_{G2}$$

$$V_O = \frac{ g_{m2}(R_{S2}||R_L) V_{G2}}{(1 + g_{m2}(R_{S2}||R_L))}$$

Therefore the voltage gain is:

$$A_{V2} = \frac{V_O}{V_{G2}} = \frac{g_{m2}(R_{S2}||R_L)}{(1 + g_{m2}(R_{S2}||R_L))} = \frac{R_{S2}||R_L}{\frac{1}{g_{m2}} +R_{S2}||R_L } = 0.786325 V/V$$

The overall voltage gain is:

$$A_V = A_{V1}*A_{V2} = -7.7V/V$$