Why is only one channel of my dual H-bridge motor driver design failing?

I have a dual motor driver board I designed for driving 2 linear actuators with 48V and each one has as rated full load current of 3.5 amps. I can expect up to 10 amp short duration on startup, but they are heavily geared worm drive actuators and can lift many hundreds of kilograms.

The issue: My issue is that one channel seems fine and is able to power up, be idle, drive the motor as intended on ONE out of two nearly identical channels (in fact can drive TWO motors on the one output just fine) but one channel in particular is blowing up very quickly on all the boards we have tried. 4 boards out of 12 tested so far have shown the failure mode.

General details I designed the board with a H-bridge driver IC and external high voltage, high current MOSFETS so they should have been able to comfortably handle the load.

The linear actuators are used intermittently. They are basically forklift up/down arm motors and are expected to be used for a few seconds to lift or lower a load and then the user drives around a bit before needing to use them again.

The system is powered by a 48V nominal LiFE-PO battery, with charged voltage sitting around 56V, and near end of charge around 40V.

NOTE: Sorry for the confusion here, but my silkscreen has M1 and M2 incorrectly labelled (swapped around) and is planned to be fixed on the revision of this board, so the "M1" on silkscreen and how it was referred to originally in this question is actually the M2A and M2B signals shown in the schematics, half of the confusion came from U1 and U2 and the signal labelling in my schematic versus what I intended for the connectors themselves in the application. I didn't realize my mistake until after the boards were made. The ACTUAL issue is from the H-bridge formed by Q3,4 Q7,8 and U1, whose output signals go to connector J4 which on the schematic show M2A and M2B but on the silkscreen on the board show as M1A and M1B.

Components of interest

N-Channel MOSFET used in the H-bridges - Nexperia BUK7275, 100V 21 amp rated. Device datasheet: https://assets.nexperia.com/documents/data-sheet/BUK7275-100A.pdf

H-bridge driver IC: Microchip MIC4606-2 (PWM input variant). 85V rated external N-channel MOSFET H-bridge driver IC. https://ww1.microchip.com/downloads/en/DeviceDoc/MIC4606-Data-Sheet-DS20005604D.pdf

Circuit:

Motor used - the 48V ones:

Failure mode pictures:

Circuit Layout - 48V distribution to each channel highlighted

Circuit layout - showing H-bridge current paths on both channels.

Circuit layout - bottom layer - ground plane also acting as heat sinking surface area

Reference design for comparison - MIC4606-2 eval board schematic

Failure Modes: 4-5 boards have failed so far, all in M1 channel.

In most situations the M1 channel doesn't fail until the load (motor) is driven by input signals from my control board, which even if they were 100% duty signals should still drive the H-bridge safely and correctly and the motors even have built-in limit switches to shut off when they reach end of travel.

At least 2 have been from power-up and not even actually trying to run the motors, even just powering up is enough to trigger the fault.

Early failures looked like they were gate voltage issues, but I confirmed with the datasheets that the 12V drive voltage and the MOSFET ratings (+-20V VGS on the gate) should all be fine.

Attempts to fix: Resistors (10k) added from gate to source to help with discharge or reducing spurious gate voltages. Did not help. Note the failed result, with pin 11 of the MIC4606-2 showing signs of case rupture.

I thought maybe the gate->source voltages were peaking above 20V and killing the gates, so I also tried 15V zener diodes across the Gate->Source pins, but then for some reason we got no functional movement of the motors (but no failures either..). Not sure what went wrong with the zeners, it may have been a red-herring and my collaborator (remote from me) made a mistake somewhere. I thought the zeners were going to be a home run.

What more should I look at for diagnosing/fixing this? What could be killing my FETs only on 1 channel, and the other is totally fine? How can I make this thing more robust?

Extra Info from questions: Scope traces showing application driving the a 12V motor at "full speed" (joystick full tilt in that direction) for Q3 gate (yellow trace) and Q8 gate (blue trace). Note Q8 is "on" to conduct to 0V for the motor, and Q3 is delivering the source power (12V for these traces) at the required duty % (around 90% duty )

Scope showing the 'start up' pulses where on the system controller start up I prime the motor drive circuit on all channels. Again this is Q3 and Q8 traces in yellow and blue respectively.

I don't see anything obviously bad going on here. Also quickly (low quality .. ) checked Q3 and Q4 for signs of cross-conduction but I couldn't see any evidence of both gates turning on at once.

Edit - proposed new schematic design with improvements and better gate protection Here's my adjusted schematics showing additional components to protect the input sides of things (for parasitic/inductive spikes on connection or power-up), including handling floating inputs to the MIC4606-2 chip, and a blocking diode on the 12V line so that 48V doesn't somehow find its way through the chip and into my control board.

The main H-bridge schematic improvements bring additional bypass and local power supply decoupling capacitors, gate pull-down resistors to keep them off if the MIC4606-2 chip releases control of the gates, gate capacitors and gate charge/discharge circuit with diode to give a 'fast' turn off.

main schematic showing input improvements to fix noload failures and startup new H-bridge circuit with gate drive improvements and bypass caps and resistors and added freewheeling diodes

• Have you checked the PWM timing at the gates? Do you have double scope traces from the complementary pairs that you could include here? Jun 18, 2021 at 5:48
• Second the scope output suggestion, and would also suggest probing 'AHB' voltage. Are you charging the bootstrap capacitor on power on? That high side drive topology requires you to start with the low side fet activated to get high side switching to work Jun 18, 2021 at 6:37
• also 100% pwm is not possible in that design, for the same reason Jun 18, 2021 at 6:42
• you need to do the opposite, hold at 0% to activate the low side fets and charge the bootstrap caps. you definitely can't do 100% duty with a bootstrap design, at least not for particularly long. Jun 20, 2021 at 5:37
• Q3 and Q8 are in Channel 2 which is fine. Whereas Q1 and Q6 are in Channel 1 which is dodgy. Could you clarify which transistors and channels you are referring to?
– tim
Jun 20, 2021 at 10:00

I don't see any bypass capacitors near your switching FETs. Glitches on the 48V line could be damaging your FETs. You need 100nF surface mount capacitors very close to the FETs and perhaps something larger nearby. You need to keep wiring inductance to a minimum on your bypass capacitors due to the fast edges (do not use thermals on the bypass capacitor pads).
Your transistors are properly placed so you can have a bypass capacitor(s) going from the source of the low-side transistor to the drain of the high-side transistor with minimal wiring inductance.

Q9 needs a resistor between gate and source, perhaps 47k to 100k, to ensure turnoff.
Q11 needs a series resistor from 12V to the gate to squash any transients on the 12V rail.
C10 should be across the zener.

Since you state that your circuit dies without a load, you have cross-conduction issues which is a sure way to kill the FETs. If you have cross conduction, you need to add dead-time to your PWM signal.
Once you sort out the cross conduction issues, start with a lower voltage for your 48V supply, perhaps 5 volts, so you don't blow stuff up.
Monitor the current on the power line feeding the FETs with an oscilloscope. If you have access to a high bandwidth AC+DC clamp-on current probe, use it.
If things are working fine at 5V, increase the voltage in steps making sure things look ok at each step.

• I think you might be the closest to the true cause/solution with the bypass caps and other generally missing stuff nearby the FETs. The MIC4606-2 handles deadtime and cross-conduction issues within its own logic, so that's not it. My PWM signals are not typical H-bridge complimentary ones, they are a little simpler than that. hold one at 0V and pulse the other one, to do speed + direction, is how this chip works. The MIC4606 layout shows quite a few passives and supporting diodes near the FETs. ibb.co/Z8Z1MTz Jun 20, 2021 at 6:42
• It's likely that the 4700pf capacitor from gate to source on each FET, and the discharge support network of resistors and diodes on each FET, make a difference in survivability. See here ibb.co/PhXNbDq Jun 20, 2021 at 6:44
• @KyranF, Adaptive dead time: "Although the adaptive dead-time circuit in the MIC4606 prevents the driver from turning both MOSFETs on at the same time, other factors outside of the anti-shoot-through circuit’s control can cause shoot-through. Other factors include ringing on the gate drive node and capacitive coupling of the switching node voltage on the gate of the low-side MOSFET." - page 22 of MC4604 datasheet.
– tim
Jun 21, 2021 at 11:16
• @tim yeah I expect my low side FET gate is ringing or otherwise having issues and may be failing under load and feedback transients. The failure of ALO1 gate signal back at the chip itself and the low side FET blowing up is a good indicator of that failure opportunity. The MIC4606-2 evaluation board schematics shows a bunch of resistors and diodes and bypass cap on each gate of their FETs. Jun 21, 2021 at 20:28
• @qrk I have not had any failures of my board running 12V loads (but they are only smaller, low load motors), but I have a 48V 500W spindle motor arriving any day now, to test this stuff myself. Please see the edit at the end of my main question for the proposed new schematics with all the components and improvements I added, do you think these will help? Jun 25, 2021 at 4:00

Here are some of my observations. One of the first things I noticed is that the PCB layout is not symmetrical, so I looked for differences between the two channels.

The group-of-four traces in the bottom layer (Fig. 1) appear to be of poor quality and very close together with possibly a short circuit. Is this really the case or just a bitmap rendering artefact? Is "signal X" the same as ALO2? You are using suffix "2" for the control signals, e.g. ALO2, but suffix "1" for the motor, i.e. M1A and M1B. Is this correct?

Figure 1 – Annotated circuit layout - bottom layer - ground plane also acting as heat sinking surface area.

Is the 48 V distribution interfering with the signal traces near Channel 1? It appears to cross over the Channel 1 control signals, circled in Fig. 2.

Figure 2 – Annotated circuit layout - 48V distribution to each channel highlighted.

It looks like a high current has passed through the trace and via, damaging the chip at point X, circled in Fig. 1 and Fig 3.

Figure 3 – Annotated pin 11 of the MIC4606-2 showing signs of case rupture.

In your updated question you provided scope traces for Q3 and Q8 which are in Channel 2. My understanding is that Channel 2 is fine, whereas Q1 and Q6 are in Channel 1 which is dodgy. Could you clarify which transistors and channels you are referring to especially with regard to the signal and motor suffixes?

The schematic you have provided doesn't match the photos of the PCBs, e.g. which channel are C4 and C8 in? Perhaps this has caused some confusion between you and your remote collaborator regarding the placement of the Zener diodes. Did your remote collaborator obtain the scope traces with a different schematic to the one you are using? What do all the control signals look like when the module is powered up?

• see the comment on the main post. The silkscreen for M1 and M2 channels is actually swapped. The H-bridge formed by Q3,4 and Q7,8 are the failing channel, which is technically the M2A/B channels, driven by IC U1. The silkscreen calls it out as M1A/M1B but as mentioned that's technically wrong. I hope that clears up some confusion. The placement of Zener diodes I got my collaborator to place them across the legs (gate to source) of all FETs just like the resistors shown, with the hope to clamp Vgs voltages to 15V or less, in case it was catastrophic gate voltage from regeneration etc Jun 20, 2021 at 23:46
• zoom in and signal labels on the bottom layer traces you asked about. Enable for Channel B just gets held high to 5V all the time, it allows the output H-bridge drives to energize. the 12V is the logic supply for chip U1 going to the capacitors between U1 and the Q7 and Q3 FETs. ibb.co/Ny1BgcR Jun 21, 2021 at 0:12
• ALO1 signal is the one which shows physical damage on the U1 chip in the image you circled in blue. That's the gate for the lowside FET Q4. See net highlight here: ibb.co/LQ64VpY Jun 21, 2021 at 0:22

When designing motor control, there should be also current sense circuit and OC (over current) detection/protection.

Transistors are mounted on minimal footprint area without thermal vias, and so on.., so you have to considerably de-rate the current capability of the MOSFETs to appox. 1A for such placement.

The main issue, as I suspect is that you do drive your motors full FWD and full BKW, which is wrong. You may never drive at 100% duty cycle, since you have a bootstrap PSU for the high side MOSFETs.

EDIT:

You do have a gate resistors for high side MOSFET 22 ohm, but none for low side. I didn't look details for the specified gate driver, but I do think the gate resistors should be the same.

EDIT 2:

Beside the small footprint area and the case that instead of pouring the entire plane you have "isolated" the footprints and connected small traces to the plane. there is also an issue of not having any bus capacitance that will store the energy, so this is truly wrong.

But there are also other facts:

• low PWM frequency 200Hz-1kHz
• the switching pattern is not known, how do you manage the regenerative braking?

The PWM frequency shall be at least Source: $$f_s\geq \frac{5}{2\pi\tau}$$

Where $$\\tau=L/R\$$

From your description is not clear on how the low side transistor is switched. For the bootstrap PSU it is needed that the low side transistor is switched ON every PWM period to charge the upper side driver supply. But here comes the catch:

If the PWM frequency is low, then the current through the motor winding is discontinuous. You switch the upper transistor ON and lower OFF, for the ON pulse duration, then you switch upper transistor OFF and you must switch the lower transistor ON for the bootstrap. At the very first moment, the current will recirculate through both lower transistors, but then the current will change the direction and the motor will start to break. This breaking energy will be converted into a heat : winding resistance + MOSFETs Rdson resistance. Probably you do waste battery energy and you convert it into a heat due to low PWM switching frequency.

For a lifting operation of DC motor, the most suitable variant would be a four quadrant mode - 4Q. For a correct operation, you should have a capacitor bank to store the regenerative energy that in turn will charge the battery.

The motor speed is almost proportional to the applied voltage, meaning that H-bridge has to mimic the ideal voltage source:

• if the source voltage is higher than motor voltage, we got motoring mode. The current flows from source to the motor
• if the source voltage is lower, then we got a generator mode. The current flows from the generator to the source.

To transform your H-bridge into this operation all 4 MOSFETs have to to switch at every PWM cycle:

• the left upper switch and left lower switch are complementary switches, if one is ON the other is OFF

• the right upper and lower are complementary switches and they work in the opposite as the left half-bridge

• If the 0V is needed then the duty cycle ratio is 50% for all four switches.

• At full FWD direction the upper right is switching at 95%, the lower right is switching at 5%, the upper left is switching at 5% and the lower left is switching at 95%.

• At full BKW direction ...

With a such sequence and with an enough high switching PWM freqency, the converter and motor will self enter into a motoring or generator mode. You should ramp up to limit the motor current, but also ramp down to dump the energy into capacitor bank - that's the way you avoid that inertial energy is converted into pure heat, rather into electrical power.

Example:

• at startup both upper transistors are OFF, and both lower transistors are ON
• at the FWD command, both left and right legs start to switch at 50/50%
• the PWM ratio is ramping up
• after the FWD command is gone, the PWM ratio is ramping down until it reaches 50/50%
• switch both upper transistors OFF, and both lower transistors ON
• That gate driver monitors the low FET's gate for it's adaptive dead time. Placing a resistor in series with the low FET's gate prevents this from working correctly. For the top FET, the chip monitors the switch node, not the gate, so the 22 ohm in series should't be a problem. The chip also has undervoltage protection on the bootstrap, so while 100% duty cycle surely is the wrong thing to do, it should not cause a blow-up. Jun 19, 2021 at 7:21
• I agree my thermal handling isn't particularly good on this board. Next revision will have some thermal vias going to the bottom for at least 1 inch ^2 copper for each net. In my application i'm not getting up to 100% duty cycle. tops out around 90%. The MIC4606 chip handles adaptive deadtime as @Unimportant mentioned above. User reports 'cool' FETs while successfully driving the 48V motors (two from the same channel as well! ) in normal operations, there doesn't seem to be a thermal issue here Jun 20, 2021 at 6:28
• also note the application here has a motor which has built-in limit switches so I wasn't worried about overcurrent, and I wanted this to be simple. I've done external current monitoring before in other projects, just didn't seem warranted for this one. As mentioned before this doesn't seem to be a load or thermal issue. There's something funky with the drive parasitics or feedback voltages, is my thought. Do you have any other ideas? Jun 20, 2021 at 6:30
• @KyranF Yes. The transistor footprint is "isolated" and then connected with tiny traces to a plane, instead to be all in one - this increases resistance. The + and - traces are far away and there is no capacitor in between. The regenerative energy has nowhere to go, so the voltage rises and breaks the MOSFEts. Jun 20, 2021 at 8:34