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I have noticed that on recent (particularly PCIe 4.0) hardware that we're starting to see some pretty interesting layout on the differential pairs. I get the basic principles of design i.e. impedance control, no sharp bends, phase tuning etc, however some of the stuff I'm seeing just doesn't make sense.

In the board pictured below, the paths of the lanes are almost deliberately zany. PCIe lanes aren't required to be of equal lengths, I don't think that's what the author of the PCB appears to be doing, so what gives?

enter image description here

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    \$\begingroup\$ I'm sure it's more than just this, but I kind of like the idea that the designer is just having a little fun... \$\endgroup\$
    – Hearth
    Commented Jun 19, 2021 at 6:06
  • \$\begingroup\$ This particular card may not be the best example, since it's not just a regular peripheral, but rather "a PCIe retimer card that plugs into a PCIe standard x16 slot, re-drives the PCIe signals to external mini-SAS HD connectors (4 total), buffers a single PCIe clock, and provides sideband USB and I2C interfaces. This card allows a traditional server to connect via external PCIe cables to another server or storage chassis that has the same external PCIe connection." - opencompute.org/products/77/wiwynn-pcie-retimer-card-p16rc \$\endgroup\$ Commented Jun 19, 2021 at 6:12
  • \$\begingroup\$ I'm aware what the card is. This kind of routing is also seen on recent Motherboards. \$\endgroup\$ Commented Jun 19, 2021 at 6:21
  • \$\begingroup\$ One possible explanation to avoid straight lines as straight copper tracks can get aligned with the PCB glassfiber weave and thus the dielectric constant varies, and that causes variation in the differential impedance. Would this be an answer or guess, I am not sure. \$\endgroup\$
    – Justme
    Commented Jun 19, 2021 at 10:41
  • \$\begingroup\$ @Justme considering how robust PCIe tends to be, that's something to consider, but unlikely. \$\endgroup\$ Commented Jun 19, 2021 at 11:06

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Aesthetic reasons, or automatic optimization:

Different PCIe lanes explicitly do not need to be length-matched. So, there's no "reason" these trace pairs need to meander a bit. There's no downside to it - no motherboard has to guarantee the lanes are length-matched, either, so length-matching them on a PCIe card is in vain.

For the length skew within one lane, you can see that the "inner" side slightly curves occasionally - to compensate for the fact that the inner side of a curve naturally becomes shorter (not convinced you have to do that for these < 8mm of difference – rule of thumb, that's less than 15 ps of length skew on a PCB, so hardly relevant for single-digit GHz signals).

Justme raised the interesting point that keeping away from 90° angles makes sure there's no systematic difference between the substrate material beneath one half of a differential par due to the glass fiber weave. I can't disprove that, but honestly, considering the unknown connectors and motherboards, and the general robustness of PCIe, it would surprise me.

So, I don't think there's really a technical reason. I agree with Hearth, when they said that a designer might simply might have had a little fun; but maybe someone says "come on, length matching, avoiding weave-alignment and a few other things can't hurt, and we have this expensive auto-router with EM simulations, so let that thing optimize" – and that thing optimized.

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  • \$\begingroup\$ PCIe lanes that are part of the same link do have a (very loose) length match requirement. The match time is the time taken for TS1. \$\endgroup\$ Commented Jun 19, 2021 at 14:43
  • \$\begingroup\$ The glass weave is the most interesting angle on this I hadn't considered. I have read about it in some layout guides (which have been around for years) but have seen very little of it until recently. I have a couple of recent ASRock motherboards with the same crazy looking PCIe lanes. It must be that designers are now taking that recommendation more seriously given the higher demands of PCIe 4.0. \$\endgroup\$ Commented Jun 19, 2021 at 16:50

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