VHDL includes commands like access ,new and shared variable that are never synthesizable or while and loop that are still somewhat synthesizable but are never recommended to to be used.

So why do they even exist if they cant be synthesized and are only limited to simulation?

  • 14
    \$\begingroup\$ Because VHDL was evolved to support verification as well. Not just design. \$\endgroup\$
    – Mitu Raj
    Jun 20, 2021 at 8:51
  • 13
    \$\begingroup\$ Fundamentally, hardware description languages (the "HDL" in VHDL) were originally meant to describe hardware, not to be synthesized into hardware. \$\endgroup\$
    – The Photon
    Jun 20, 2021 at 15:31
  • \$\begingroup\$ @ThePhoton make that an answer. \$\endgroup\$
    – user253751
    Jun 21, 2021 at 13:58
  • \$\begingroup\$ shared variable is synthesizable for dual-port rams \$\endgroup\$
    – Ben
    Jun 24, 2021 at 1:22

2 Answers 2


Those parts of VHDL exist for use in testbenches.

Being able to simulate a VHDL design under a VHDL testbench is an essential step in the VHDL development process.

Verification is proving a design under a testbench that checks the design for expected behaviour and complains about deviations from it.

Verification is always recommended, even for small or tiny designs, but it is often mandatory. This may be under the rules of the company you work for or under the requirements of the market it's for e.g. military, aviation, safety.

Verification is essential for ASIC developments and so almost always mandatory.

So the capability to support complex and thorough testbenches is not a 'nice to have' in VHDL - it's as essential as supporting synthesis.

I would always simulate and prove a VHDL design under a testbench before trying it in a CPLD or FPGA. Simulation is where you aim to find and fix problems. Hardware testing is where you aim to prove the design, not debug it.

  • \$\begingroup\$ Debugging in a screen with a keyboard is indeed much faster! ... and then it turns out the thing you're integrating with sometimes has glitches where it goes outside the documented characteristics, and you have to take that into account, so you end up debugging in hardware anyway. Just sayin'. :-D \$\endgroup\$
    – Jon Watte
    Jun 20, 2021 at 17:32
  • 1
    \$\begingroup\$ @JonWatte, note my careful use of 'aim' :-) If you have enough understanding of the behaviour of the circuitry connected to the target device, you can prove in simulation completely. If that's behaviour's not understood, you have to debug on the system. But you aim for the former, you do as much as you possibly can on the simulator because you can find things on average far quicker. That's been my experience, over a lot of devices in a lot of applications over a lot of years. I always put input pins through filters/stages that assume the worst, within the available gates and clock speed. \$\endgroup\$
    – TonyM
    Jun 20, 2021 at 17:43

Hardware Description Languages (HDLs), of which VHDL and Verilog are prime examples, are used for a variety of purposes related to the definition, design and verification of hardware systems.

To describe each purpose:


A behavioral model of a component or system. The response of the model to external stimulus defines a design, but it isn't required to be able to directly build (synthesize) hardware from this level of description. For example, you could have a VHDL behavioral model of a RAM component, useful for simulation, yet the actual implementation of the RAM may be independent, such as from a transistor-level layout.


Used to directly control the implementation of the hardware. Most digital ICs are designed at Register Transfer Level (RTL), either in Verilog or VHDL. There are Electronic Design Automation (EDA) tools to synthesize and place and route these designs to implement them in a form that can be manufactured by a semiconductor fab.


To verify design correctness, the design is included in a "testbench", which also may include other components that the design would communicate with. The testbench would provide stimulus and check response, as TonyM described. The testbench and models of other components would be defined in an HDL, but it's not necessary for them to be synthesizable.


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