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Why is the output of stateful elements often named Q?

A register has D (data) as input and Q as output.
What does the Q stand for? I'm having a hard time searching for it.


Q represents the output of a flip-flop or register. For an edge-triggerred flip-flop, the clock-to-Q time is the time it takes for the register output to be in a stable state after a clock edge occurs.

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  • \$\begingroup\$ One nuance: suppose the clock changes at t=0. Clock-to-Q delay is the time d when Q may start to change. Q does not necessarily settle at time d. \$\endgroup\$ – sqd Apr 7 at 4:28

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