I am currently working on an Arduino to NIOS II Compiler that I am using on GitHub. I have provided a link to the compiler here: https://github.com/dimag0g/nios_duino. The issue I am having is that I am unable to compile my top level file because of two errors, one of them regarding syntax and the other regarding module declaration.
Below is my code for my top level module:
/* *FPGA Interconnect Module for the NVSRAM Database, SRAM PUF, & UI *SRAM PUF connected through GPIO pins to parallel IO *NVSRAM database connected through GPIO pins to I2C module *User Interface connect through UART/USB to NIOS */ module sawblade_project ( input wire CLOCK_50_B5B, // Clock signal input wire [35:0] GPIO, // I/O pins for input wire LEDR0, // Connect to PIO 13 to verify the code is working output wire UART_TX, // UART ports for UI computer input wire UART_RX // Uart ports for UI computer ); //tie SRAM_VCC_CNTRL high, BLE low & BHE high always begin GPIO = 1; //SRAM_VCC_Control tied high GPIO = 0; //BLE tied low (active low) GPIO = 1; //BHE tied high (active low) end //instantiate nios_duino module nios_duino u0 ( .clk_0_ext_clk(CLOCK_50_B5B), //Clock signal @ 50 MHz .clk_in_reset_reset_n(KEY1), //Clock reset signal .cpu_reset_cpu_resetrequest(KEY0), //CPU Reset request signal .cpu_reset_cpu_resettaken(LEDR1), //CPU Reset taken signal .i2c_0_ext_sda_in(GPIO), //SDA for NVSRAM database .i2c_0_ext_scl_in(GPIO), //SCL for NVSRAM database .i2c_0_ext_sda_oe(1), //I2C data buffer tied high .i2c_0_ext_scl_oe(1), //I2C clock buffer tied high .pio_0_ext_export[12:0](GPIO[12:0]), //GPIO to PIO IP .pio_0_ext_export(LEDR0), //LED signal @ PIO 13 to ensure compiler operation .pio_0_ext_export[19:14](GPIO[18:13]), //GPIO to PIO IP .pio_0_ext_export[30:20](GPIO[31:21]), //GPIO to PIO IP .pio_0_ext_export(GPIO), //GPIO to PIO IP .uart_0_ext_rxd(UART_RX), //UART receiving line for UI interface .uart_0_ext_txd(UART_TX) //UART transmission line for UI interface ); endmodule
This time, I made sure not to compile either the template files that came with my project once I generated the code using the Platform Designer (SOPC Builder). Nevertheless, I am still receiving this error from the compiler:
Error (10170): Verilog HDL syntax error at sawblade_project.v(31) near text: "["; expecting ")". Check for and fix any syntax errors that appear immediately before or at the specified keyword.
Could this error be because I am not instantiating the pio_0_ext_export bus correctly, or is there another issue entirely?
In addition I am also having a module declaration error with one of the submodules:
Error (10228): Verilog HDL error at nios_duino_sysid_qsys_0.v(34): module "nios_duino_sysid_qsys_0" cannot be declared more than once
However, I have checked the code for this submodule and that does not appear to be the case, especially since this submodule code was generated by the Platform Designer and was not edited by me. Here is the code for the nios_duino_sysid_qsys_0 module for reference:
// (C) 2001-2018 Intel Corporation. All rights reserved. // Your use of Intel Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files from any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Intel Program License Subscription // Agreement, Intel FPGA IP License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Intel and sold by // Intel or its authorized distributors. Please refer to the applicable // agreement for further details. //Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your //use of Altera Corporation's design tools, logic functions and other //software and tools, and its AMPP partner logic functions, and any //output files any of the foregoing (including device programming or //simulation files), and any associated documentation or information are //expressly subject to the terms and conditions of the Altera Program //License Subscription Agreement or other applicable license agreement, //including, without limitation, that your use is for the sole purpose //of programming logic devices manufactured by Altera and sold by Altera //or its authorized distributors. Please refer to the applicable //agreement for further details. // synthesis translate_off `timescale 1ns / 1ps // synthesis translate_on // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module nios_duino_sysid_qsys_0 ( // inputs: address, clock, reset_n, // outputs: readdata ) ; output [ 31: 0] readdata; input address; input clock; input reset_n; wire [ 31: 0] readdata; //control_slave, which is an e_avalon_slave assign readdata = address ? 1623863076 : 17149200; endmodule