# What's the saturation speed of a transistor and the wires between inside a modern CPU?

I'm tinkering with a specialized CPU design and I'd like to calculate/estimate the saturation time of a circuit that may eventually be part of a CPU made with current technology.
For this I need to know:
How long do I need to provide signal to a transistor for it to saturate?
How long it takes for the wires between to propagate a signal?
Do I have to maintain the signal on the wire the entire time for it to propagate a signal?
Assuming optimal temperatures

• If you want your transistor to switch as quickly as possible, you don't want it to fully saturate. Commented Jun 22, 2021 at 0:16
• @The Phantom it's just over 50% of the saturation time, correct? Commented Jun 22, 2021 at 0:21
• The question about transistors is the kind of thing that SPICE simulators are meant to answer. The question about how the signal propagates on the wire is an entirely different question. It would be better to post it separately. Commented Jun 22, 2021 at 0:24
• Interesting CPU design, the ones I am familiar with are MOS.
– Gil
Commented Jun 22, 2021 at 2:11
• @Gil MOS is the type of transistor about which I'm inquiring. Commented Jun 22, 2021 at 2:25

I'm tinkering with a specialized CPU design and I'd like to calculate/estimate the saturation time of a circuit that may eventually be part of a CPU made with current technology.

Then you need to do what real CPU designers do: simulate it. Most tools will provide gate-level simulation which is accurate enough. For specialized purposes you can also do physical-level simulation with SPICE.

For this I need to know: How long do I need to provide signal to a transistor for it to saturate?

The gate of a FET is effectively a capacitor; the time taken is that to charge the capacitor to an acceptable level so that the voltage level on the output of the gate has risen to a threshold, such as 80% or 90% of VDD ("rise delay" / "fall delay").

How long it takes for the wires between to propagate a signal?

It depends. Usually the Elmore Delay Model is good enough; in order to use that you need to first select your silicon process then ask the vendor what the resistance and capacitance per unit length of wire are.

Do I have to maintain the signal on the wire the entire time for it to propagate a signal?

Usually the wires on a chip are short enough that the answer is "yes". It's not like a transmission line between chips, where you can send pulses, it's more like a funny-shaped capacitor that you have to pour charge into in order to raise/lower its voltage to a target level.

• Thank you for the plethora of information. I have gate level simulations, the issue that I have with them is the use of and gates as switches, at the chip level those would be a single transistor to allow passage rather than the two used in a gate. As I'm typing this I realize that I just need a new simulator. Is spice the industry standard for gate level simulations? I like mine (circuitverse) because it exports the gate simulation to Verilog so I can load it onto an FPGA. Commented Jun 22, 2021 at 16:03
• You probably do need a new simulator; but note that doing design with pass transistors probably isn't synthesizable onto FPGAs. Commented Jun 23, 2021 at 7:56
• (unless you specifically try to synthesize a pass transistor, an AND gate will be a NAND gate with an inverter on it, ie six transistors, or in a FPGA it will be a lookup table) Commented Jun 23, 2021 at 8:12
• Correct, Hence the original question, which your answer has helped me to solve. I'm close to being able to make a quick approximation by hand. With this I calculated a nand gate at a few ps which is close enough for my work. Commented Jun 23, 2021 at 20:30