Is it possible to configure the STM32 SPI peripheral such that MISO data is latched on the same clock edge where MOSI data is loaded? Usually (for CPOL=1 and CPHA=1) MOSI updates on the falling edge and on the rising edge MOSI is valid and MISO is latched. (Specifically the STM32L052, but seems to be universal).

My peripheral wants to latch MOSI on the rising edge, but its output data is valid on the falling edge. This device uses half-duplex mode with a single data line. The STM32 ties MISO and MOSI together in this mode. It seems like the STM32 only supports latching on the same edge for both devices. The available modes just change the polarity and which edge is used for both input and output.

STM32 SPI timing

I am trying to interface with the proprietary 3-wire interface on the Maxim MAX3948. This initially looks like I2C but its not. Its more like half-duplex SPI with an address and CS for flow control.

MAX3948 serial timing

I don't require fast IO with this device. Would I be better off just bit-banging it rather than trying to get the SPI peripheral to handle a non-standard protocol?

  • \$\begingroup\$ What prevents you from changing the sampling edge when transmission is ended and reception starts? \$\endgroup\$
    – Justme
    Jun 22, 2021 at 8:22
  • \$\begingroup\$ I had not thought about it this way. Unfortunately it doesn't quite work out. If I try to flip CPOL between write and read I get an extra clock edge when I change the polarity that messes up the sequence. I tried just using CPOL=0 and flipping CPHA but it gives me an extra long clock cycle before the data word. \$\endgroup\$
    – Mike
    Jun 24, 2021 at 0:42


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