I recently found two designs for an XOR gate.
(Edit: original pic had error in the labels of XOR gate 1.)
They both appear to be CMOS. That is, they both use an equal number of nMOS and pMOS transistors, and pMOS comes directly from Vdd and nMOS comes directly from ground, so they should not have any pull-down or pull-up issues respectively.
So are they both equally suitable for "chaining up" logic gates? Do they have any real advantages/disadvantages over each other?
(Note, the gates could be anything in combinational logic. I'm not using only NAND or only NOR.)
The reason I'm asking this question is because I don't know all the side-effects to watch out for in circuits. All circuits are analogue in practice. I'm aware that pMOS should not try to pull down, and nMOS should not try to pull up. Other than that, the only other side-effects I'm aware of are propagation delay and voltage drop, so after a certain number of gates (or transistors themselves), you insert a buffer which is just two not gates on a unique power circuit.