I recently found two designs for an XOR gate.

enter image description here

(Edit: original pic had error in the labels of XOR gate 1.)

I numbered them as type 1 and type 2. I found them at these youtube videos: Vid 1, Vid 2. They are short but you can jump to the end to see them fully drawn.

They both appear to be CMOS. That is, they both use an equal number of nMOS and pMOS transistors, and pMOS comes directly from Vdd and nMOS comes directly from ground, so they should not have any pull-down or pull-up issues respectively.

So are they both equally suitable for "chaining up" logic gates? Do they have any real advantages/disadvantages over each other?

(Note, the gates could be anything in combinational logic. I'm not using only NAND or only NOR.)

The reason I'm asking this question is because I don't know all the side-effects to watch out for in circuits. All circuits are analogue in practice. I'm aware that pMOS should not try to pull down, and nMOS should not try to pull up. Other than that, the only other side-effects I'm aware of are propagation delay and voltage drop, so after a certain number of gates (or transistors themselves), you insert a buffer which is just two not gates on a unique power circuit.

  • 1
    \$\begingroup\$ FYI, nMOS labels for your type 1 are incorrect. As is, there is always a path to VSS. Hint: A and A' should be on the left hand side. \$\endgroup\$
    – Greg
    Jun 23, 2021 at 22:25
  • 1
    \$\begingroup\$ @Greg Yeah I see that now. Interesting but i can't find an arrangement that works in all cases. E.g., on the bottom half, swap A' with B, but now for the inputs 00 and 11, the XOR output line is always "disconnected" from Vdd and Vss. I think this is dangerous and ambiguous to leave it floating. It should be driven by the Vss to a low voltage. Edit: nm, found it, swap A' with B, then swap A with A', and it should work. \$\endgroup\$
    – DrZ214
    Jun 24, 2021 at 0:23

1 Answer 1


I would guess that the version on the right might be slightly faster than the one on the left. The version on the right has only two source/drain nodes (instead of four) at each internal node, so changing the voltages of those internal nodes should be faster. The version on the left will also require a metal wire connection for the internal nodes while the one on the right might not, further decreasing the capacitance.

Without actually creating a layout it's hard to tell which of either would be smaller, but if I had to bet my own money I would bet that the version on the right is smaller because it doesn't need the metal straps for the internal nodes.

By the way, your assumption that a two-inverter buffer is always added after some number of gates is incorrect.

  • \$\begingroup\$ Thank you, but can you explain why the two-inverter buffer is not always needed? I thought for sure sooner or later the voltage signal will degrade. What other way is there but to buffer it with "fresh" power source? If it's not easily answerable, i'm happy to ask a new question about it. \$\endgroup\$
    – DrZ214
    Jun 24, 2021 at 0:12
  • \$\begingroup\$ No, the signal does not degrade if fully complementary CMOS gates are used. The signal coming out of the 100th NAND gate in a chain has the same voltages as the signal coming out of the first NAND gate. If you have read otherwise, give us a link or citation. \$\endgroup\$ Jun 24, 2021 at 11:52

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