I'm using a 74LVC245 buffer, which is a 3.3V chip with 5V tolerant inputs. What will happen if one of the chip's outputs is enabled and is connected to an external device with a 2K pull-up resistor to 5V? I welcome suggestions on other ways to do this, but I'm mainly interested in analysis of what happens with this specific setup.
The 74LVC245 datasheet states that the voltage range applied to any output in the high or low state must be between -0.5V and VCC + 0.5V. There's also a footnote that says the output negative-voltage rating may be exceeded if the output current rating is observed. I assume this refers to the output clamp current, which is -50 mA for Vo less than 0V.
Here's where I'm confused. Whether the D0 output is either driving high or low, there will be a voltage drop across R1. Won't that keep the voltage at D0 always within the range allowed by the datasheet? If D0 is outputting a logical low value, the voltage will be 0V and current will be -2.5 mA (5 / 2K). If D0 is outputting a logical high value, the voltage will be 3.3V and current will be -0.85 mA (1.7 / 2K).
I'm particularly unsure about what happens when D0 is a logical high value at 3.3V. Current will be flowing into D0 - where does it go, and through what structure in the chip? Is there a clamp diode to the 3.3V supply here? The fact that the datasheet gives a spec for max clamp current below 0V but not above 3.3V makes me think there is not a positive clamp diode. So does the current just flow into the 3.3V supply through the output transistor? Is it likely to cause problems to have a small backfeed current like this, or is 0.85 mA too small for most worries? If it matters, this is a hobby-level project, not a scientific application requiring stringent specs.