Altium tries to approximate circles where it doesn't need to.

I have a polygon pour with some vias inside, associated to the same net. The connection style is "direct connection" so the copper should be continuous between the pour region and the via pad.

Altium approximates a circle with zero distance between them in the polygon which results in an imperfect connection that impacts both thermal and electrical resistance:

imperfect polygon connection

Reducing the arc approximation settings in polygon properties makes the connection better but doesn't solve the problem entirely. The imperfection is more obvious if the board is manufactured with relatively low standards.

  • Why doesn't it pour over the pad smoothly?
  • How should I make proper via connections to polygons?

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I can make it a clean connection by increasing the via pad size by a notch, AFTER I've poured the polygon, so it over-covers the copper, but the next pour and it happens again. That's not a "solution" for sure.

  • \$\begingroup\$ What exact settings are you using to get that? Here is what a via should look like. \$\endgroup\$ Commented Jun 25, 2021 at 14:55
  • \$\begingroup\$ I guess there's something wrong in the clearance rules, i.e. the polygon to hole clearance is larger than the pad size. \$\endgroup\$
    – asdfex
    Commented Jun 25, 2021 at 15:02
  • 1
    \$\begingroup\$ I've been using Altium for 20 years, laid down millions of vias. This has never happened. Are you using the stock pre-defined vias, or did you define something custom??? \$\endgroup\$
    – Kyle B
    Commented Jun 25, 2021 at 15:06

1 Answer 1


The problem was some sketchy rules in clearance which were imported from the KiCad importer. Apparently the KiCad importer is mapping direct connections to zero-mm clearanced normal connections.

I just deleted all imported rules and made some of my own and the connections are now perfect.


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