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I am currently in the process of designing a 24V to 5V buck converter using the TI LM3150 buck converter (datasheet). I designed the buck converter to meet the following operating parameters:

Vin = 6-30V
Vout = 5V @ 12A

I used the TI Webench to generate a design following these criteria. The generated schematic and steady state simulation results are below:

enter image description here

V_out

However, when the design is exported and imported into Cadence Orcad, the Pspice transient simulation shows a different resulting output voltage:

enter image description here

enter image description here

When executing the transient simulation, there are convergence errors for some of the voltages and currents. To remedy this issue, I enabled auto convergence and the simulation ran successfully. I have attempted to change the step sizes for ABSTOL and VNTOL attributes but the conflicting simulation results persist.

enter image description here

Is it possible that the PSpice in Orcad does not work the same as in TI-TINA or is this behavior caused by another issue?

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    \$\begingroup\$ I can promise you that PSpice does not work the same as TINA, and I can further suggest that you're probably using vastly different models of the LM3150, and possibly also for the switching transistors. \$\endgroup\$
    – Hearth
    Jun 26, 2021 at 17:38
  • \$\begingroup\$ @Hearth I find that odd. I have also attempted associate the pspice model from TI's support page for the LM3150, instead of the one imported along with the schematic from Webench and I still get the same results. Is there a way to rectifying this issue or is it recommended to use TI's software to simulate their components? \$\endgroup\$
    – R_Fabek
    Jun 26, 2021 at 17:53
  • \$\begingroup\$ Given that one method gives you results similar to what you would expect, and the other encounters numerical errors and can't simulate at all, I would trust the one that can actually run the simulation. I'm sure it's possible to fix it, I just don't know how and don't have the time or energy to figure out how. \$\endgroup\$
    – Hearth
    Jun 26, 2021 at 17:55

2 Answers 2

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User wiring error on FB (grounded) will cause over-voltage on output in Pspice.

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    \$\begingroup\$ Just to add this this (faster reply) The two simulations are different and the main issue is the feedback... the PSPICE has the feedback signal tied to GND instead of at R6:R7 junction \$\endgroup\$
    – user16222
    Jun 26, 2021 at 18:09
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The pspice sim has the fb loop tied to ground. Also the mosfet models should match our you shouldn't expect the same results.

Even after all that the solvers are most likely different and will give different results.

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