I am new to the world of HDL. I am currently working on implementing AES in Verilog code.
I manage the flow of my logic using varying FSMs. Given this approach I currently have to wait for the first block to finish processing before inputting the next one.
To improve throughput, I want to perform pipelining so I can input a new block every N clock cycles. However, I can't fathom how I would use both FSM and pipelining. Given I use a register to track the current state, if I pass a new input in this will overwrite the state for the previous input.
Is it possible to use an FSM and pipelining in unison?
Given the below code, I cannot generate a new output every clock cycle. This is because the second input cannot go through the FSM before until the first completes. This is a simplified example of what I am trying to achieve.
`timescale 1ns / 1ps
module pipeline_multiplier(
input [15:0] a,
input [15:0] b,
input clk,
input rst,
output reg [31:0] c
);
reg [15:0] a_temp, b_temp;
reg [31:0] c_temp;
parameter [1:0]
Pipe1=2'b00,
Pipe2=2'b01,
Pipe3=2'b10;
reg [1:0] state = Pipe1;
always @(posedge clk)
begin
if(rst)
begin
state = Pipe1;
end
else
begin
case(state)
Pipe1:
begin
a_temp <= a;
b_temp <= b;
state <= Pipe2;
end
Pipe2:
begin
c_temp <= a_temp * b_temp;
state <= Pipe3;
end
Pipe3:
begin
c <= c_temp;
state <= Pipe1;
end
endcase
end
end
endmodule