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I'm working with the TDA7266D dual bridge audio amp.

https://www.st.com/en/audio-ics/tda7266d.html#documentation

The datasheet indicates that the device can operate with VCC between 3.5V and 12V. I'm running nominally at 5V and the output signal is fine. What I would like to do is kick up the voltage to around 9V to get a bigger output swing for the speaker. However as I increase the voltage the output signal rises, but diminishes and flattens. Looking at pin 7 IN1 (at the IC pin) I can see that the bias on the input doesn't change with the increase in voltage. Is VREF fixed for this part? Is that the reason the output signal is getting quashed? Has anyone had success with running this part with higher voltages?

The circuit I have is identical to the circuit shown on page one of the datasheet except I'm only driving one speaker with OUT1.

TDA7266D Example Circuit Diagram

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    \$\begingroup\$ The Vref at pin7 should be half the supply voltage. Maybe your input coupling capacitor leaks current? Maybe the IC is defective? \$\endgroup\$
    – Audioguru
    Jun 27 at 14:43
  • \$\begingroup\$ How are your input sources connected and what are they? Maybe you do need both speakers wired in for it to work properly? \$\endgroup\$
    – Andy aka
    Jun 27 at 16:32
  • \$\begingroup\$ I lifted pins 7 and 14 and varied VCC between 3.5V and 12V. The VREF seems to remain at around 1.6V, which makes sense because we would necessarily want to have to change the input signal swing with a rise in VCC. With an input sinusoid connected to pin 7, turning up VCC past 5.5V causes the output voltages at pins 2 and 5 to rise, and differentially diminish down to about 400mV. I'm not able to get a voltage swing more than 4.5V out of the device. No response yet from ST tech support. \$\endgroup\$
    – bit_slicer
    Jul 2 at 16:02
  • \$\begingroup\$ @Andy aka I'm using a waveform generator as input. I can vary the input amplitude and watch the output hit the rails and square off. With VCC at around 9.5V the rails look like about 400mV. I did try loading both outputs. No change. \$\endgroup\$
    – bit_slicer
    Jul 2 at 18:46

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