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For decoupling we just use a capacitor like 1 uF bulk and 0.1 uF ceramic caps at each power pin. But how are these values calculated? How many caps do we need to use in parallel? Can anyone explain it with examples from a datasheet or similar? It seems odd, but I can’t get clarity on it.

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  • \$\begingroup\$ Which explanation do you or not understand? Impedance or time response or frequency attenuation of ESR + Xc & SRF with a transient load spectrum or switched equivalent impedance. It helps to know what you already know. \$\endgroup\$ Jun 27 at 16:10
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    \$\begingroup\$ Although calculating in some instances could be important, generally speaking it's not really worthwhile. You just follow the general rules of thumb, and sprinkle these around in the manners mentioned below. Why? Because these caps are very inexpensive - Much cheaper to have 10-20% more caps than 'really necessary' compared to the cost of having some spurious crazy problems with a board design which then needs debug and redesign. That ends up costing MORE in schedule delays and engineers time than a few hundred thousand fractional-penny devices. \$\endgroup\$
    – Kyle B
    Jun 28 at 5:14
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    \$\begingroup\$ One paradigm is for the decoupling capacitors to provide a low impedance path from power to ground at frequencies from when the power supply is ineffective up to whatever the IC needs. §12.12 of High-Speed Signal Propagation has an example. \$\endgroup\$
    – 7efkvNEq
    Jun 28 at 8:06
  • \$\begingroup\$ Generally, the datasheet for the component tells you what values to use for decoupling capacitors. Look at that first, and follow its instructions. \$\endgroup\$
    – Cody Gray
    Jun 29 at 9:25
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Basically you want something close enough to the pin that at the edge rates in play the bounce is not too bad, and then something further away with (possibly) enough ESR to damp everything to keep the far higher ESL of the supply wiring from screwing things up.

ESL is the critical thing, not in the first instance capacitance and that is almost wholly driven by package geometry.

Generally that means an 0603 or 0402 close to the package pin, and value does not really matter all that much, so as 100nF is readily available, cheap, and every assembly house has a MONSTER reel of them on the feeder, that is what you use, 10n/100n/1u, it mostly don't really matter.

Numbers of caps are driven by the desire to minimise the loop areas (Loop area rises inductance), and frankly we all mostly over do it (sometimes hugely) because the things cost basically nothing, and the time wasted if you need another one and don't have a place to put it is NOT free.

For really extreme boards PDN simulation is a thing, basically using electromagnetics field solvers to optimise cap placement for lowest noise, but unless you are doing something like a server motherboard it is so expensive that just shotgunning a few extra decoupling caps around is cheaper and easier.

One common trap (That you even see on datasheets and app notes!) is something like a couple of values in parallel and only a decade apart, often the resulting resonant impedance peak will be most unwelcome.

Spice some stuff with reasonable parasitics including reasonable trace inductances, ESR and ESL and you will discover wonders, it is an exercise that is totally worth the time.

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    \$\begingroup\$ If you want to avoid resonance between parallel capacitors you want to keep the values closer together not further apart. The recommendation from Murata is no more than a decade apart, for example. \$\endgroup\$
    – The Photon
    Jun 27 at 17:34
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    \$\begingroup\$ @ThePhoton Or go a long way apart and pick a big part that has sufficient ESR! Low ESR is NOT always the way to go, sometimes the fact that a jellybean electrolytic has an ohm or so of ESR is just what you need. If you are going less then a decade apart, why bother? Interestingly you can buy MLCCs with specified levels of ESR, for exactly the damping they provide. \$\endgroup\$
    – Dan Mills
    Jun 27 at 20:21
  • \$\begingroup\$ There are reverse geometry caps for really low ESL (0204, 0306, 0508 for example). Very useful with really fast switching devices. \$\endgroup\$ Jun 29 at 11:04
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tl; dr: it’s not just about the cap values, but their parasitics too.

The data-driven technical answer is, you model it if you have access to the very expensive power integrity software that takes into account the entire physical design and all its parasitics, including those of the capacitors. You optimize the design to achieve the desired target power impedance, while minimizing all the loop areas for the bypassed devices. The software is hundreds of thousands of dollars, and driving it to an accurate result is many months of work. For a complex, high-volume, aggressive-schedule project it could be worth it.

For the rest of us, you follow some time-honored rules of thumb, taking into account some knowledge of capacitor behavior and mis-behavior (like anti-resonance and bias effect.)

A couple of those ‘rules of thumb’:

Small caps work best for high frequency because their parasitics are smaller. They’re most effective when the board layout keeps the inductance to a minimum. That’s why they’re placed close to pins.

0.1uF has proven to offer a good balance between parasitics and capacity for frequencies of interest at the board level. Some designers will mix 0.1uF with larger and smaller values to achieve a wider frequency response, but this must be done with care to avoid anti-resonance. This can be modeled using SPICE or one of its free alternatives (e.g., LTSpice) using models provided by the manufacturer.

This brings up another 'rule of thumb': When mixing values, use 5 - 10x spacing to avoid anti-resonance. This is why they chose 0.1 + 1uF: they're far enough away from each other that their resonance peaks don't interact (much, anyway.)

Quick-and-dirty, you can use the KEMET K-SIM tool to simulate combined cap values and how their resonances interact. Try it here: https://ksim3.kemet.com/capacitor-simulation

That all said, here’s a good Murata guide to that stuff. https://www.murata.com/~/media/webrenewal/support/library/catalog/products/emc/emifil/c39e.ashx

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  • \$\begingroup\$ I thought the point of these in circuit designs was to be parasitic. You substitute in active power from a supply for when the reactive power supplied from the capacitor is too low. \$\endgroup\$
    – tuskiomi
    Jun 28 at 15:10
  • \$\begingroup\$ That doesn’t make sense. The point of decoupling is to reduce the impedance of the supply, shunting the large dI/dt switching noise locally at the device. This not only reduces loop area, but makes the caps more effective. The supply inductance outside of the shunted loops then can be helpful instead of harmful. The fact that the caps themselves (as well as their connection to the board) have parasitics is why we bother with mixing values at all. \$\endgroup\$ Jun 28 at 16:11
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how these values are calculated?

Question: How do we calculate how big a shovel should be?

Answer:\$\text{ }\text{ }\$ We don't; pretty much all shovel makers make the same size because, through years of experience in making, selling and using shovels and, the freedom of information transfer, a size equivalent to a capacitance of 100 nF is about right.

Of course, shovels come with variations in size and some folk will use 10 nF capacitors on each IC supply rail but, the reason may be purely what stock item they have or, it may be driven by the 10 nF circuit generating higher frequencies (and higher frequency supply currents) and therefore, better capacitors with higher self-resonant frequencies are a sensible choice. 10 nF has a higher self-resonance than 100 nF all other things being equal.

How many caps we need use in parallel?

Well, I think you've answered that when you said "0.1uF ceramic caps at each power pin".

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    \$\begingroup\$ I like this analogy; we use 0.1uF not because someone calculated that value to be the "right" amount, but because it's a good round number that's close enough most of the time. \$\endgroup\$
    – spuck
    Jun 28 at 17:13
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If you want to know the specific minimum capacitance and maximum ESL and ESR you need or can get away with, you need to take into account the component requirements PCB layout and geometry of the traces. And since placing capacitors changes the PCB layout and traces it can become a recursive problem. In other words, no simple pen and paper calculations here. This is simulation territory.

More generally though, what you need to know is the IC's edge speed, voltage tolerances, transient current requirements, and approximately the trace inductance leading to the IC.

You want the total capacitance high enough so that the voltage tolerances don't spike or dip beyond IC tolerances at the low frequencies, but you want the inductance low enough so that the high frequency currents don't have to take long return paths around the board which produces noise and EMI. This means you need to look at the capacitor impedance curves and target the appropriate impedance at the key frequencies of operation to make sure the inductance is low enough. Placing capacitors in parallel properly increases capacitance and reduces the overall parasitic inductance which helps the high charge demand low frequency currents and inductance sensitive high frequency currents.

Placing multiple capacitors different values can make things worse because each capacitor is capacitance with a parasitic inductance and when they are different they can resonate with each other to produce noise peaks which makes things worse if your IC operating frequencies falls on those peaks.

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Murata - Application Manual for Power Supply Noise Suppression and Decoupling for Digital ICs

https://www.murata.com/~/media/webrenewal/support/library/catalog/products/emc/emifil/c39e.ashx

This is 85 page application manual provides information about the theory and practice of decoupling. The decoupling devices are characterized by a practical measure called insertion loss. The insertion loss of various bypass capacitor values is shown under specified test conditions.

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