Why isn't my common emitter amplifier working properly?

I simulated this common emitter amplifier in LTSpice:

However, instead of an amplified sine wave, the voltage at the output looks like this:

Would someone be able to explain why this is happening? Thanks.

• What happens if you run the simulation for much longer...say 100m instead of 10u? Commented Jun 28, 2021 at 4:54
• Discuss how it is that you designed this circuit. What's the quiescent operating point, for example? And why did you decide to have only about 50 mV across your emitter resistor? That's very close to the dynamic emitter resistance! Why are you driving a capacitive load? And what's all that stuff on the left before getting to the BJT? Explain, please.
– jonk
Commented Jun 28, 2021 at 5:04
• @jonk Yeah I have to say, I'm still a novice at amplifier design (if that isn't evident already) so forgive me if I say anything stupid. I designed it by following these instructions: instructables.com/How-to-Design-Common-Emitter-Amplifier Commented Jun 28, 2021 at 5:55
• @jonk C4 isn't a load (or it's not supposed to be at least). It's there to stop DC signals from passing through (i.e. the 6 volts supplied to the amplifier). Ditto for all the other 10 uF capacitors in the circuit. Commented Jun 28, 2021 at 6:02
• @jonk In real life, R1 and R2 would be a 500K potentiometer that should be used to adjust the amplitude of the output. Commented Jun 28, 2021 at 6:04

3 Answers

Your circuit had its R3 and R4 resistances too high and with the wrong ratio.

Your frequency is 1.5MHz that is 1500 times higher than my 1kHz. Therefore my C2 is 1500 times higher (70.5uF) than your 0.047uF. C2 reduces the output signal to almost zero.

• The 1.5MHz circuit modified today is completely different to the 1kHz circuit I answered to last year. The original 47nF C3 is only 70.5 ohms at 1.5MHz and the 1k collector resistor barely pulls it positively but the transistor can pull it down negatively. Commented Mar 9, 2023 at 14:47

You could try this.

The gain is specified for a load of 5k to cater for the possibility of a following stage having an input resistance of 5k. To increase the gain, increase the resistance value of RL.

• Please provide a link or citation for the graphic you copied into your question. The policy for this site is that we provide attribution to the original creator. Thanks. Commented Jun 28, 2021 at 11:32
• @ElliotAlderson I designed the circuit and created the graphic myself using Circuit Wizard.
– user173271
Commented Jun 28, 2021 at 12:46

For a nominal hFE of 200 (+400% /-50%);

Rb= hFE Re = 200 * 47 = 8 k. This is in parallel with R4 = 100k so the base bias voltage is reduced by this input load.

You are only looking at the initial capacitor charging voltage step (inverted).

The problem is the base voltage bias is regulated by hFE and the low Re from “Load Regulation” error of the high bias R Values. The equivalent Rb ought to be <= 100 x Re and lower is better regulated which affects low frequency response of input RC time constant.

a far better solution is to use negative feedback to help regulate the collector voltage and current for wide tolerances on hFE yet only need to reduce the base Req to about 8k or 200x Re so you can get away with slightly lower bias as it self-regulates a bit.

Now looking like an inverting Op Amp gain defined by Rfb/Rin ratios with low open loop gain, you can use Cin as your Rin if you want but the current gain increases with collector current but the. The voltage gain Reduces with collector current using Rfb due to negative feedback, so there is a sweet spot in the 100 to 200 Re range. The concept is far better than the classic H bridge CE amplifier taught in school because this reduces the variation in Vbe , which means the the nonlinear quadratic THD distortion on an asymmetric sine wave is significantly improved according to how much excess gain you feedback.

You can short out the 40 ohms but then you need a small pull-down R on the base to reduce the feedback bias current going into the base to raise the collector voltage to mid way.

• examine the Rfb/Zi Ratio and expect gain to be about half at best if you are drawing enough current. This design is good for a gain of 20 if input and output impedance safe similar and up to 50 or more if you lower the input impedance relative to output such as shorting Re)

Here is a solution with a V gain of 22 and adjustable nFE from 100 to 800 with an adjustable Vin from 100mVpp and up. The Vpp probes indicate the signal levels so it is easy to see the Voltage gain with 100mVpp input.

BTW C1 is redundant.

• Here I did what I suggested , lowered the Re to 1 Ohms which required a 10x bigger input cap, and adding Rs of 50 ohms for a Rfb/Rin=50k/50=1000 ratio but my voltage gain is only about 150. That’s a lot better than any H bias CE amp and the output is stable but some pull down changes are need with a wide variation of Vcc to improve the collector Vq without attenuating the gain too much. tinyurl.com/yevrrbom There are formulae are on this site for this configuration. Commented Jun 28, 2021 at 11:18
• I chose a feedback DC current about 3 x the base current for stability and attenuation compromise. Commented Jun 28, 2021 at 11:24
• That link in your answer is an amazingly good depiction of how a CE amplifier works. It would be super useful as a teaching aid for EE students. Commented Jun 4, 2022 at 19:19
• Down-voters please comment. Commented Mar 9, 2023 at 8:06