In the below image,there's the code for parity generation. State represented by even_odd and output as z. What will happen if the circled red part as in the image has blocking assignments instead of nonblocking? Will verilog start executing the 2nd always block (the one triggered by change in even_odd) without finishing the execution of 1st always block?
It would make a difference if you changed the first
always to blocking assignments to
even_odd and used the value of
z on code that followed the
Verilog does not guarantee the order of execution between statements executing in parallel processes. This allows for optimizations that allow
z become the same signal, effectively eliminating the second
always process. So you would have a race condition using blocking assignments.
You would also have a race condition if
even_odd went to any other
always @(posedge clk) process and tried to read it.