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In the below image,there's the code for parity generation. State represented by even_odd and output as z. What will happen if the circled red part as in the image has blocking assignments instead of nonblocking? Will verilog start executing the 2nd always block (the one triggered by change in even_odd) without finishing the execution of 1st always block?

enter image description here

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    \$\begingroup\$ Interesting question. The example posted is not good to illustrate it though, as the "blocking" assignments in it won't actually block anything and probably won't change the behavior. \$\endgroup\$
    – Eugene Sh.
    Jun 28 '21 at 15:53
  • \$\begingroup\$ If I assume there are other statements in the always block, then what will happen? \$\endgroup\$ Jun 28 '21 at 16:59
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    \$\begingroup\$ I would really help to post the code as text, not a picture of it. \$\endgroup\$
    – dave_59
    Jun 28 '21 at 17:16
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It would make a difference if you changed the first always to blocking assignments to even_odd and used the value of z on code that followed the case statement.

Verilog does not guarantee the order of execution between statements executing in parallel processes. This allows for optimizations that allow even_odd and z become the same signal, effectively eliminating the second always process. So you would have a race condition using blocking assignments.

You would also have a race condition if even_odd went to any other always @(posedge clk) process and tried to read it.

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