I wanted to find the capacitance at X,Y,P and Q in the diagram given below. Idea was to find the dynamic power consumption of the circuit and for that we need the capacitance(I got this idea from a IEEE paper 'StrongARM Latch'). Is there any method to get the capacitance using simulation and also get the capacitance using some formula or calculation? I know the dimension of the transistors used. It would be great if you can suggest a method that I could use for this circuit as well as any general circuit. I am sorry if the question is vague, please lemme know if any more information is needed. enter image description here EFFECTIVE CIRCUI WHILE CHARGING LTSPICE SIMULATION



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Capacitance, like voltage, is not defined "at a point"; it is defined between two points.

In a VLSI circuit the capacitances include parasitic capacitances to all of the surrounding structures as well as junction capacitances and gate capacitances. Some of these vary with applied voltage.

The right way to do this is to create an actual layout and use your design tools to extract the capacitances for each node.

  • \$\begingroup\$ How can I do that? I am using LTSPICE, is it possible in that? Oh I think I got what you meant by two points. But then I think working of this latch is such that capacitors are charged when CK=0. At that time M7 will be OFF and thus will the capacitance remain constant ? then can I say Cx ,Cy etc ? will that make sense @Elliot \$\endgroup\$ Commented Jun 28, 2021 at 17:52
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    \$\begingroup\$ You need to use a VLSI layout tool, such as Cadence or Silvaco. Your SPICE schematic does not contain all of the capacitances in the circuit, so there is no way that SPICE can determine their value. These capacitances must be extracted from the actual physical layout of the transistors and wiring, then added to the schematic. And how can capacitances charge or discharge if the voltage across them remains constant? \$\endgroup\$ Commented Jun 28, 2021 at 18:07
  • \$\begingroup\$ Can you please check the new image I added? In the paper he just said that the capacitance will be charged when CK=0. and this will be the reason for dynamic power consumption \$\endgroup\$ Commented Jun 28, 2021 at 18:15
  • \$\begingroup\$ I'm not sure if you are using "charged" as a verb or an adjective here, but that's beside the point. You don't know the values of the capacitances. You need a physical layout from which you can extract those values. SPICE can not do that. If you want to use SPICE without the extracted parasitics that's your decision, but it won't be as accurate. \$\endgroup\$ Commented Jun 28, 2021 at 18:26
  • \$\begingroup\$ For example, there is capacitance from the source/drain to the substrate. This is a PN junction capacitance (unless you are using SOI) that depends on the voltage between the source/drain and the substrate but also on the physical area of the source drain region. Do you know the area of your sources and drains? \$\endgroup\$ Commented Jun 28, 2021 at 18:27

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